Low Skew, 1-to-6, 854S006 Differential-to-LVDS Fanout Buffer Datasheet Description Features The 854S006 is a low skew, high performance 1-to-6, Six differential LVDS outputs Differential-to-LVDS fanout buffer. The CLK, nCLK pair can accept One differential clock input pair most standard differential input levels. The 854S006 is CLK, nCLK pair can accept the following differential input characterized to operate from either a 2.5V or a 3.3V power levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL supply. Guaranteed output and part-to-part skew characteristics Maximum output frequency: 1.7GHz make the 854S006 ideal for those clock distribution applications Translates any single-ended input signal to LVDS levels with demanding well defined performance and repeatability. resistor bias on nCLK input Output Skew: 55ps (maximum) Propagation delay: 850ps (maximum) Additive phase jitter, RMS: 0.067ps (typical) Full 3.3V or 2.5V supply -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment Q0 nCLK 1 24 GND nQ0 CLK 2 23 GND Pull-up Q1 CLK V 3 22 V DD DD Pull-down nCLK nQ1 V 4 21 V DDO DDO Q0 5 20 nQ5 Q2 nQ0 6 19 Q5 nQ2 GND 7 18 GND Q3 17 Q1 8 nQ4 nQ3 nQ1 9 16 Q4 Q4 10 15 VDDO VDDO Q2 11 14 nQ3 nQ4 12 13 nQ2 Q3 Q5 nQ5 2017 Integrated Device Technology, Inc. 1 April 11, 2017854S006 Datasheet Pin Descriptions Table 1. Pin Descriptions a Number Name Type Description 1 nCLK Input (PD) Inverting differential clock input. 2 CLK Input (PU) Non-inverting differential clock input. 3, 22 V Power Positive supply pins. DD 4, 10, 15, 21 V Power Output supply pins. DDO 5, 6 Q0, nQ0 Output Differential output pair. LVDS interface levels. 7, 18, 23, 24 GND Power Power supply ground. 8, 9 Q1, nQ1 Output Differential output pair. LVDS interface levels. 11, 12 Q2, nQ2 Output Differential output pair. LVDS interface levels. 13, 14 Q3, nQ3 Output Differential output pair. LVDS interface levels. 16, 17 Q4, nQ4 Output Differential output pair. LVDS interface levels. 19, 20 Q5, nQ5 Output Differential output pair. LVDS interface levels. a Pull-up (PU) and pull-down (PD) refer to internal input resistors, and are indicated in parentheses. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN Function Tables Table 3. Clock Input Function Table Inputs Outputs CLK nCLK Q 0:5 nQ 0:5 Input-to-Output Mode Polarity 0 1 LOW HIGH Differential to Differential Non-Inverting 1 0 HIGH LOW Differential to Differential Non-Inverting a 0Biased LOW HIGH Single-ended to Differential Non-Inverting a 1Biased HIGH LOW Single-ended to Differential Non-Inverting a Biased 0 HIGH LOW Single-ended to Differential Inverting a Biased 1 LOW HIGH Single-ended to Differential Inverting a Refer to the Application Information section, Wiring the Differential Input to Accept Single-ended Levels. 2017 Integrated Device Technology, Inc. 2 April 11, 2017