854S712 1:2 Fanout Buffer with Pre-Emphasis Datasheet Description Features The 854S712 is a differential, high-speed 1:2 data/clock fanout buffer 1:2 differential data/clock fanout buffer and line driver and line driver. The outputs support pre-emphasis in order to drive 4.5 Gbps data rate (NRZ) (maximum) backplanes and long transmission lines while reducing inter-symbol Differential LVDS outputs interference effects. The pre-emphasis level is configurable to Differential input supporting LVDS, LVPECL and CML levels optimize for low bit error rate or power consumption. Pre-emphasis utilizes an increased output voltage swing for transition bits. Configurable output pre-emphasis Low-skew outputs: 10ps (maximum) The device is optimized for data rates up to 4.5 Gbps (NRZ) and for Low data deterministic jitter: 4ps (maximum) deterministic jitter in data applications and low additive jitter in clock LVCMOS interface levels for the control inputs applications. The outputs are LVDS-compliant while the differential input is compatible with a variety of signal levels such as LVDS, Asynchronous output disable into high-impedance state LVPECL and CML. Internal input termination, a bias voltage output Internal input termination: 100(Differential) for AC-coupling and small packaging (VFQFN) supports Additive phase jitter, RMS: 0.08ps (typical) space-efficient board designs. The 854S712 operates from a 3.3V power supply and supports the industrial temperature range of -40C Full 3.3V supply voltage to +85C. -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Pin Assignment Block Diagram nOE0 PE0 16 15 14 13 Q0 1 12 Q0 IN nQ0 IN 11 2 nQ0 VTT 50 854S712 nIN Q1 10 3 Q1 VREF AC 8XXXXXX 50 V TT nQ1 9 4 nQ1 nIN 5 6 78 nOE1 PE1 V VBB REF A 16-pin,3mmx3mmVFQFNPackage C 2017 Integrated Device Technology, Inc. 1 October 10, 2017 GND GND nOE0 PE0 nOE1 PE1 V DD V DD854S712 Datasheet Pin Description and Pin Characteristic Tables Table 1 Pin Description Number Name Type Description Non-inverting differential data and clock input. LVDS, LVPECL or CML interface 1 IN Input levels. 50 to V TT. Inverting differential data and clock input. LVDS, LVPECL or CML interface levels. 4nIN Input 50 to V TT. nOE0, 6, 7 Input Pulldown Output enable control. LVCMOS/LVTTL interface levels. nOE1 15, 14 PE0, PE1 Input Pulldown Pre-emphasis control. LVCMOS/LVTTL interface levels. 12, 11 Q0, nQ0 Output Differential output pair. LVDS interface levels. 10, 9 Q1, nQ1 Output Differential output pair. LVDS interface levels. Output Bias voltage reference for AC-coupling. 3V REF AC Center tap for input termination. Leave floating for LVDS input, connect to 50 to GND 2V TT for LVPECL inputs and to the V output for AC-coupled applications. REF AC 5, 16 GND Power Power supply ground. 8, 13 V Power Power supply pins. DD NOTE: Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 2pF IN R Input Pulldown Resistor 51 k PULLDOWN 2017 Integrated Device Technology, Inc. 2 October 10, 2017