62.5MHz to 250MHz, 1:4 LVCMOS/ 86004-01 Data Sheet LVTTL Zero Delay Clock Buffer GENERAL DESCRIPTION FEATURES Four LVCMOS/LVTTL outputs, 7 typical output impedance The 86004-01 is a high performance 1-to-4 LVCMOS/LVTTL Clock Buffer and a member of the family of High Performance Single LVCMOS/LVTTL clock input Clock Solutions from IDT. The 86004-01 has a fully integrated CLK accepts the following input levels: LVCMOS or LVTTL PLL and can be con gured as zero delay buffer and has an input and output frequency range of 62.5MHz to 250MHz. The external Output frequency range: 62.5MHz to 250MHz feedback allows the device to achieve zero delay between the Input frequency range: 62.5MHz to 250MHz input clock and the output clocks. The PLL SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass External feedback for zero delay clock regeneration mode, the reference clock is routed around the PLL and into the with con gurable frequencies internal output divider. Fully integrated PLL Cycle-to-cycle jitter, (F SEL = 1): 45ps (maximum) Output skew: 60ps (maximum) Supply Voltage Modes: (Core/Output) 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V 5V tolerant input -40C to 70C ambient operating temperature CONTROL INPUT FUNCTION TABLE Available in lead-free (RoHS 6) package Input/Output Input Frequency Range (MHz) F SEL Minimum Maximum 0 125 250 1 62.5 125 BLOCK DIAGRAM PIN ASSIGNMENT 86004-01 16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm package body G Package Top View 2016 Integrated Device Technology, Inc 1 Revision D January 21, 201686004-01 Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 3, Q1, Q0, Output Clock outputs. 7 typical output impedance. LVCMOS/LVTTL interface levels. 13, 15 Q3, Q2 2, 7, 14 GND Power Power supply ground. Frequency range select input. When LOW, I/O frequency range is from 4 F SEL Input Pulldown 125MHz to 250Mz. When HIGH, I/O frequency range is from 62.5MHz to 125MHz. LVCMOS/LVTTL interface levels. 5V Power Core supply pin. DD 6 CLK Input Pulldown LVCMOS/LVTTL clock input. 8V Power Analog supply pin. DDA Selects between the PLL and reference clock as input to the dividers. 9 PLL SEL Input Pullup When LOW, selects the reference clock (PLL Bypass). When HIGH, selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels. Feedback input to phase detector for regenerating clocks with zero delay. 10 FB IN Input Pulldown Connect to one of the outputs. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset 11 MR Input Pulldown causing the outputs to go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. 12, 16 V Power Output supply pins. DDO NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN V , V = 3.465V 23 pF Power Dissipation Capacitance DD DDO C PD (per output) V , V = 2.625V 17 pF DD DDO R Output Impedance 3.3V 5% 5 7 12 OUT TABLE 3. CONTROL INPUT FUNCTION TABLE Input/Output Input Frequency Range (MHz) F SEL Minimum Maximum 0 125 250 1 62.5 125 2016 Integrated Device Technology, Inc 2 Revision D January 21, 2016