VDDOB ICS87004I-03 LVCMOS/ LVTTL Fanout Buffer/ Divider DATA SHEET General Description Features The ICS87004I-03 is a low skew, 1, 2 3, 4 5, 6 8, 16 Two banks of two LVCMOS/LVTTL outputs LVCMOS/LVTTL Fanout Buffer/Divider. The ICS87004I-03 has Selectable LVCMOS/LVTTL clock inputs selectable clock inputs that accept single ended input levels. Output LVCMOS CLK supports the following input types: LVCMOS, enable pin controls whether the output is in the active or high LVTTL impedance state. Maximum output frequency: 250MHz Output skew: 40ps (typical) The ICS87004I-03 is characterized at 3.3V, 2.5V and mixed 3.3V,2.5V, 3.3V,1.8V, 2.5V,1.8V input/output supply operating Bank skew: 20ps (typical) modes.Guaranteed bank, output, and part-to-part skew Part-to-part skew: 60ps (typical) characteristics make the ICS87004I-03 ideal for those applications Power supply modes: demanding well defined performance and repeatability. CORE / OUTPUT 3.3V / 3.3V 3.3V / 2.5V 3.3V / 1.8V 2.5V / 2.5V 2.5V / 1.8V -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Pin Assignment Block Diagram Pullup OEA V 1 20 OEA DD 3 NA2 2 19 VDDOA Pulldown NA2:NA0 NA1 3 18 QA0 NA0 4 17 QA1 N Output Divider CLK0 5 16 GND NA2:NA0 CLK SEL 6 15 QB1 0 0 0 1 (default) CLK1 7 14 QB0 0 0 1 2 QA0 NB2 8 13 0 1 0 3 NB1 9 12 GND 0 1 1 4 Pulldown CLK SEL NB0 10 11 OEB QA1 1 0 0 5 1 0 1 6 ICS87004I-03 V 1 1 0 8 DD0A Pulldown CLK0 0 1 1 1 16 20-Lead TSSOP 6.50mm x 4.40mm x 0.925mm package body Pulldown N Output Divider CLK1 G Package 1 NB2:NB0 V DD0B Top View 0 0 0 1 (default) 0 0 1 2 QB0 0 1 0 3 0 1 1 4 QB1 1 0 0 5 1 0 1 6 1 1 0 8 1 1 1 16 3 Pulldown NB2:NB0 Pullup OEB ICS87004BGI-03 REVISION A FEBRUARY 22, 2012 1 2012 Integrated Device Technology, Inc.ICS87004I-03 Data Sheet LVCMOS/LVTTL FANOUT BUFFER/DIVIDER Table 1. Pin Descriptions Number Name Type Description 1V Power Power supply pin. DD 2, 3, 4 NA2, NA1, NA0 Input Pulldown N divider select pins for Bank A outputs. LVCMOS / LVTTL interface levels. 5, 7 CLK0, CLK1 Input Pulldown Single-ended clock inputs. LVCMOS / LVTTL interface levels. 6 CLK SEL Input Pulldown Input clock selection. LVCMOS / LVTTL interface levels. See Table 6. 8, 9, 10 NB2, NB1, NB0 Input Pulldown N divider select pins for Bank B outputs. LVCMOS / LVTTL interface levels. Output enable control input for Bank B outputs. LVCMOS / LVTTL interface 11 OEB Input Pullup levels. See Table 5. 12, 16 GND Power Power supply core ground. 13 V Power Bank B output supply pin. DDOB 14, 15 QB0, QB1 Output Single-ended Bank B clock outputs. LVCMOS / LVTTL interface levels. 17, 18 QA1, QA0 Output Single-ended Bank A clock outputs. LVCMOS / LVTTL interface levels. 19 V Power Bank A output supply pin. DDOA Output enable control input for Bank A outputs. LVCMOS / LVTTL interface 20 OEA Input Pullup levels. See Table 4. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN R Input Pulldown Resistor 51 k PULLDOWN R Input Pullup Resistor 51 k PULLUP V = V = 3.465V 10 pF DDOA DDOB Power Dissipation Capacitance C V = V = 2.625V 10 pF PD DDOA DDOB (per output) V = V = 1.95V 10 pF DDOA DDOB V = V = 3.3V 5% 17 DDOA DDOB R Output Impedance V = V = 2.5V 5% 20 OUT DDOA DDOB V = V = 1.8V 0.15V 28 DDOA DDOB ICS87004BGI-03 REVISION A FEBRUARY 22, 2012 2 2012 Integrated Device Technology, Inc.