8L3010ANLGI Renesas

IDT8L3010I Crystal or Differential to LVCMOS/ LVTTL Clock Buffer DATASHEET Description Features The IDT8L3010I is a low skew, 1-to-10 LVCMOS / LVTTL Fanout Ten LVCMOS / LVTTL outputs up to 200MHz Buffer. The low impedance LVCMOS/LVTTL outputs are designed to Differential input pair can accept the following differential input drive 50 series or parallel terminated transmission lines. levels: LVPECL, LVDS, HCSL The IDT8L3010I is characterized at full 3.3V and 2.5V, mixed Crystal Oscillator Interface 3.3V/2.5V, 3.3V/1.8V, 3.3V/1.5V, 2.5V/1.8V and 2.5V/1.5V output Crystal input frequency range: 10MHz to 40MHz operating supply modes. The input clock is selected from two Output skew: 50ps (maximum) 3.3V/3.3V differential clock inputs or a crystal input. The differential input can Additive RMS phase jitter: 0.24ps (typical) 3.3V/3.3V be wired to accept a single-ended input. The internal oscillator circuit is automatically disabled if the crystal input is not selected. Synchronous output enable to avoid clock glitch Power supply modes: Core / Output 3.3V / 3.3V 2.5V / 2.5V 3.3V / 2.5V 3.3V / 1.8V 3.3V / 1.5V 2.5V / 1.8V 2.5V / 1.5V 5V input tolerance -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment 24 23 22 21 20 19 18 17 GNDO GNDO 25 16 GND GND 26 15 IDT8L3010I nCLK1 nCLK0 27 14 32 Lead VFQFN CLK1 CLK0 28 13 5mm x 5mm 0.925mm package body XTAL OUT SEL1 29 12 NL Package SEL0 30 11 XTAL IN Top View OE 31 10 VDD GNDO GNDO 32 9 12345678 . IDT8L3010ANLGI November 30, 2018 1 2018 Integrated Device Technology, Inc. Q0 Q9 VDDO VDDO Q1 Q8 GNDO GNDO Q2 Q7 VDDO VDDO Q3 Q6 Q4 Q5IDT8L3010I Datasheet CRYSTAL OR DIFFERNTIALTO LVCMOS/LVTTL CLOCK BUFFER Table 1. Pin Descriptions Number Name Type Description 1, 3, 5, 7, 8, Q0, Q1, Q2, Q3, Q4 Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. 17, 18, 20, 22, 24 Q5, Q6, Q7, Q8, Q9 Power Output supply pins. 2, 6, 19, 23 V DDO 4, 9, 16, GNDO Power Power supply output ground. 21, 25, 32 15, 26 GND Power Power supply core ground. Power Power supply pin. 10 V DD 11, XTAL IN, Crystal oscillator interface. XTAL IN is the input, XTAL OUT is the Input 12 XTAL OUT output. 13 CLK0 Input Pulldown Non-inverting differential clock. Pullup/ 14 nCLK0 Input Inverting differential clock. Internal resistor bias to V /2. DD Pulldown Pullup/ 27 nCLK1 Input Inverting differential clock. Internal resistor bias to V /2. DD Pulldown 28 CLK1 Input Pulldown Non-inverting differential clock. Input clock selection. LVCMOS/LVTTL interface levels. 29, 30 SEL1, SEL0 Input Pulldown See Table 3A. 31 OE Input Pulldown Output enable. LVCMOS/LVTTL interface levels. See Table 3B. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units Input Capacitance 4pF C IN Input Pulldown Resistor 51 k R PULLDOWN R Input Pullup Resistor 51 k PULLUP = 3.465V 13 pF V DDO = 2.625V 12 pF V Power Dissipation Capacitance DDO C PD (per output) = 2V 10 pF V DDO = 1.65V 9 pF V DDO = 3.3V 5% 14 V DDO V = 2.5V 5% 17 DDO R Output Impedance OUT V = 1.8V 0.2V 30 DDO V = 1.5V 0.15V 55 DDO IDT8L3010ANLGI November 30, 2018 2 2018 Integrated Device Technology, Inc.