Crystal or Differential-to-LVCMOS/ 8L30210 Datasheet LVTTL Clock Buffer Description Features The 8L30210 is a low skew, 1-to-10 LVCMOS / LVTTL Fanout Ten LVCMOS / LVTTL outputs up to 200MHz Buffer. The low impedance LVCMOS/LVTTL outputs are designed Differential input pairs can accept the following differential input to drive 50 series, or parallel terminated transmission lines. levels: LVPECL, LVDS, HCSL The 8L30210 is characterized at full 3.3V, 2.5V, and mixed Crystal oscillator interface 3.3V/2.5V, 3.3V/1.8V, 3.3V/1.5V, 2.5V/1.8V and 2.5V/1.5V output Crystal input frequency range: 10MHz to 40MHz operating supply modes. The input clock is selected from two Additive RMS phase jitter: 30fs (typical) differential clock inputs or a crystal input. The differential inputs Synchronous output enable to avoid clock glitch can be wired to accept a single-ended input. The internal oscillator circuit is automatically disabled when the crystal input is Power supply modes: de-selected. Core / Output 3.3V / 3.3V 2.5V / 2.5V 3.3V / 2.5V 3.3V / 1.8V 3.3V / 1.5V 2.5V / 1.8V 2.5V / 1.5V Supports case temperature up to 105C -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram 00 01 1x 2017 Integrated Device Technology, Inc. 1 July 27, 20178L30210 Datasheet Pin Assignments 32 31 30 29 28 27 26 25 Q0 1 24 Q9 V 2 23 V DDO DDO Q1 3 22 Q8 4 GNDO 21 GNDO 8L30210 Q2 5 20 Q7 V 6 DDO 19 V DDO Q3 7 18 Q6 Q4 8 17 Q5 9 10 11 12 13 14 15 16 32-pin,5mmx5mmVFQFNPackage Pin Characteristics a Table 1. Pin Descriptions Number Name Type Description 1 Q0 Output Single-ended clock output. LVCMOS/LVTTL interface levels. 2V Power Output power supply pin for Bank A. DDO 3 Q1 Output Single-ended clock output. LVCMOS/LVTTL interface levels. 4 GNDO Power Power supply output ground. 5 Q2 Output Single-ended clock output. LVCMOS/LVTTL interface levels. 6V Power Output power supply pin for Bank A. DDO 7 Q3 Output Single-ended clock output. LVCMOS/LVTTL interface levels. 8 Q4 Output Single-ended clock output. LVCMOS/LVTTL interface levels. 9 GNDO Power Power supply output ground. 10 V Power Power supply pin. DD 11 XTAL IN Input Crystal oscillator interface. XTAL IN is the input. 12 XTAL OUT Input Crystal oscillator interface. XTAL OUT is the output. 13 CLK0 Input Pulldown Non-inverting differential clock. Pullup/ 14 nCLK0 Input Inverting differential clock. Internal resistor bias to V /2. DD Pulldown 15 GND Power Power supply core ground. 2017 Integrated Device Technology, Inc. 2 July 27, 2017 GNDO GNDO V OE DD XTAL IN SEL0 XTAL OUT SEL1 CLK0 CLK1 nCLK0 nCLK1 GND GND GNDO GNDO