Quad-Frequency Programmable IDT8N3QV01 Rev G VCXO DATA SHEET General Description Features The IDT8N3QV01 is a Quad-Frequency Programmable VCXO with Fourth generation FemtoClock NG technology very flexible frequency and pull-range programming capabilities. Programmable clock output frequency from 15.476MHz to The device uses IDTs fourth generation FemtoClock NG 866.67MHz and from 975MHz to 1,300MHz technology for an optimum of high clock frequency and low phase Four power-up default frequencies (see part number order 2 noise performance. The device accepts 2.5V or 3.3V supply and is codes), reprogrammable by I C packaged in a small, lead-free (RoHS 6) 10-lead Ceramic 5mm x 2 I C programming interface for the output clock frequency, APR 7mm x 1.55mm package. and internal PLL control registers Besides the 4 default power-up frequencies set by the FSEL0 and Frequency programming resolution is 435.9Hz N 2 FSEL1 pins, the IDT8N3QV01 can be programmed via the I C Absolute pull-range (APR) programmable from 4.5 to interface to any output clock frequency between 15.476MHz to 754.5ppm 866.67MHz and from 975MHz to 1,300MHz to a very high degree of One 2.5V or 3.3V LVPECL differential clock output precision with a frequency step size of 435.9Hz N (N is the PLL Two control inputs for the power-up default frequency output divider). Since the FSEL0 and FSEL1 pins are mapped to 4 independent PLL M and N divider registers (P, MINT, MFRAC and LVCMOS/LVTTL compatible control inputs N), reprogramming those registers to other frequencies under RMS phase jitter 156.25MHz (12kHz - 20MHz): control of FSEL0 and FSEL1 is supported. The extended 0.487ps (typical) temperature range supports wireless infrastructure, tele- RMS phase jitter 156.25MHz (1kHz - 40MHz): communication and networking end equipment requirements. The 0.614ps (typical) device is a member of the high-performance clock family from IDT. 2.5V or 3.3V supply voltage modes -40C to 85C ambient operating temperature Available in Lead-free (RoHS 6) package Block Diagram Pin Assignment PFD FemtoClock NG Q P OSC N & VCO 10 9 nQ VC 1 VCC LPF 1950-2600MHz 8 OE 2 nQ 7 114.285 MHz VEE 3 Q 6 4 5 MINT, MFRAC 2 A/D VC 7 25 7 IDT8N3QV01 Rev G Pulldown FSEL1 10-lead Ceramic 5mm x 7mm x 1.55mm Configuration Register (ROM) Pulldown FSEL0 package body (Frequency, APR, Polarity) CD Package Pullup SCLK 2 Top View I C Control Pullup SDATA Pullup OE IDT8N3QV01GCD REVISION A MARCH 6, 2012 1 2012 Integrated Device Technology, Inc. SCLK FSEL0 FSEL1 SDATAIDT8N3QV01 Rev G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-VCXO Table 1. Pin Descriptions Number Name Type Description VCXO Control Voltage input. The control voltage versus frequency 1 VC Input characteristics are set by the ADC GAIN 5:0 register bits. Output enable pin. See Table 3A for function. LVCMOS/LVTTL interface 2 OE Input Pullup levels. 3V Power Negative power supply. EE Default frequency select pins. See the Default Frequency Order Codes 5, 4 FSEL1, FSEL0 Input Pulldown section. LVCMOS/LVTTL interface levels. 6, 7 Output Differential clock output. LVPECL interface levels. Q, nQ 8 Power Positive power supply. V CC 2 9 Input/Output Pullup SDATA I C data input. Input: LVCMOS/LVTTL interface levels. Output: Open drain. 2 10 Input Pullup SCLK I C clock input. LVCMOS/LVTTL compatible interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units FSEL 1:0 , SDATA, SCLK 5.5 pF C Input Capacitance IN VC 10 pF R Input Pullup Resistor 50 k PULLUP R Input Pulldown Resistor 50 k PULLDOWN IDT8N3QV01GCD REVISION A MARCH 6, 2012 2 2012 Integrated Device Technology, Inc.