Quad-Frequency Programmable XO IDT8N4Q001 REV G DATA SHEET General Description Features The IDT8N4Q001 is a Quad-Frequency Programmable Clock Fourth generation FemtoClock NG technology Oscillator with very flexible frequency programming capabilities. The Programmable clock output frequency from 15.476MHz to device uses IDTs fourth generation FemtoClock NG technology for 866.67MHz and from 975MHz to 1,300MHz an optimum high clock frequency and low phase noise performance. Four power-up default frequencies (see part number order 2 The device accepts 2.5V or 3.3V supply and is packaged in a small, codes), re-programmable by I C lead-free (RoHS 6) 10-lead ceramic 5mm x 7mm x 1.55mm package. 2 I C programming interface for the output clock frequency and internal PLL control registers Besides the four default power-up frequencies set by the FSEL0 and 2 FSEL1 pins, the IDT8N4Q001 can be programmed via the I C Frequency programming resolution is 435.9Hz N interface to output clock frequencies between 15.476MHz to One 2.5V, 3.3V LVDS clock output 866.67MHz and from 975MHz to 1,300MHz to a very high degree of Two control inputs for the power-up default frequency precision with a frequency step size of 435.9Hz N (N is the PLL LVCMOS/LVTTL compatible control inputs output divider). Since the FSEL0 and FSEL1 pins are mapped to four independent PLL divider registers (P, MINT, MFRAC and N), RMS phase jitter 156.25MHz (12kHz - 20MHz): 0.253ps reprogramming those registers to other frequencies under control of (typical), integer PLL feedback configuration FSEL0 and FSEL1 is supported. The extended temperature range RMS phase jitter 156.25MHz (1kHz - 40MHz): 0.263ps supports wireless infrastructure, telecommunication and networking (typical), integer PLL feedback configuration end equipment requirements. Full 2.5V or 3.3V supply modes -40C to 85C ambient operating temperature Available in Lead-free (RoHS 6) package Block Diagram Pin Assignment PFD FemtoClock NG Q P OSC N & VCO nQ LPF 1950-2600MHz DNU 1 8 V DD f XTAL OE 2 7 nQ GND 3 6 Q MINT, MFRAC 2 25 7 Pulldown FSEL1 Configuration Register (ROM) Pulldown IDT8N4Q001 FSEL0 (Frequency, APR, Polarity) 10-lead ceramic 5mm x 7mm x 1.55mm Pullup package body SCLK 2 I C Control Pullup CD Package SDATA Top View Pullup OE IDT8N4Q001GCD REVISION A MARCH 6, 2012 1 2012 Integrated Device Technology, Inc. FSEL0 4 10 SCLK FSEL1 5 9 SDATAIDT8N4Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO Table 1. Pin Descriptions Number Name Type Description 1 DNU Do not use. 2 OE Input Pullup Output enable pin. See Table 3A for function. LVCMOS/LVTTL interface levels. 3 GND Power Power supply ground. Default frequency select pins. See the Default Frequency Order Codes section. 5, 4 FSEL1, FSEL0 Input Pulldown LVCMOS/LVTTL interface levels. 6, 7 Output Differential clock output. LVDS interface levels. Q, nQ 8 Power Power supply pin. V DD 2 9 Input Pullup SDATA I C Data Input. LVCMOS/LVTTL interface levels. 2 10 Input Pullup SCLK I C Clock Input. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 5.5 pF IN R Input Pullup Resistor 50 k PULLUP R Input Pulldown Resistor 50 k PULLDOWN Function Tables Table 3A. OE Configuration Input OE Output Enable 0 Outputs Q, nQ are in high-impedance state. 1 (default) Outputs are enabled. NOTE: OE is an asynchronous control. Table 3B. Output Frequency Range Output Frequency Ranges 15.476MHz to 866.67MHz 975MHz to 1,300MHz NOTE: Supported output frequency range. The output frequency can be programmed to any frequency in this range and to a precision of 218Hz or better. IDT8N4Q001GCD REVISION A MARCH 6, 2012 2 2012 Integrated Device Technology, Inc.