8P34S1102I Datasheet 1:2 LVDS Output 1.8V Fanout Buffer Description Features The 8P34S1102I is a high-performance differential LVDS fanout Two low skew, low additive jitter LVDS output pairs buffer. The device is designed for the fanout of high-frequency, One differential clock input pair very low additive phase-noise clock and data signals. Differential CLK, nCLK pairs can accept the following The 8P34S1102I is characterized to operate from a 1.8V power differential input levels: LVDS, CML supply. Guaranteed output-to-output and part-to-part skew Maximum input clock frequency: 1.2GHz characteristics make the 8P34S1102I ideal for those clock distribution applications demanding well-defined performance Output skew: 3ps (typical) and repeatability. One differential input and two low skew Propagation delay: 400ps (maximum) outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the Low additive phase jitter, RMS f = 156.25MHz, REF differential device input. The device is optimized for low power 12kHz20MHz: 42fs (typical) consumption and low additive phase noise. Maximum device current consumption (I ): 48mA EE Full 1.8V supply voltage Lead-free (RoHS 6), 16-Lead VFQFN packaging -40C to 85C ambient operating temperature Block Diagram Pin Assignment V DD 12 11 10 9 Q0 CLK nQ0 nc 13 8 V REF nCLK Q1 nc 14 7 nCLK nQ1 nc 15 6 CLK GND 16 5 VDD V 1 2 3 4 V REF REF 8P34S1102I 16-lead VFQFN 3mm x 3mm x 0.925mm package body 1.7mm x 1.7mm ePad Size NL Package Top View 2020 Renesas Electronics Corporation 1 September 4, 2020 GND nQ1 nc Q1 nc nQ0 nc Q08P34S1102I Datasheet Pin Description and Pin Characteristic Tables a Table 1. Pin Descriptions Number Name Type Description 1, 16 GND Power Power supply ground. 2, 3, 4, 13, 14, 15 nc Unused Do not connect. 5 V Power Power supply pins. DD 6 CLK Input Pulldown Non-inverting differential clock/data input. Pulldown/ 7 nCLK Input Inverting differential clock input. Pullup Bias voltage reference. Provides an input bias voltage for the CLK, nCLK input 8 V Output pair in AC-coupled applications. Refer to Figures 2B and 2C for applicable REF AC-coupled input interfaces. 9, 10 Q0, nQ0 Output Differential output pair 0. LVDS interface levels. 11, 12 Q1, nQ1 Output Differential output pair 1. LVDS interface levels. a Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 2 pF IN R Input Pulldown Resistor 51 k PULLDOWN R Input Pullup Resistor 51 k PULLUP Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, V 4.6V DD Inputs, V -0.5V to V + 0.5V I DD Outputs, I O Continuous Current 10mA Surge Current 15mA Input Sink/Source, I 2mA REF Maximum Junction Temperature, T 125C J,MAX Storage Temperature, T -65C to 150C STG a ESD - Human Body Model 2000V Note 1. ESD - Charged Device Model 1500V a According to JEDEC JS-001-2012/JESD22-C101E. 2020 Renesas Electronics Corporation 2 September 4, 2020