LVDS Frequency-Programmable IDT8N4S270 Crystal Oscillator DATASHEET General Description Features The IDT8N4S270 is a Factory Frequency-Programmable Crystal Fourth generation FemtoClock NG technology Oscillator with very flexible frequency programming capabilities. The Factory-programmable clock output frequency from 15.476MHz to device uses IDTs fourth generation FemtoClock NG technology for 866.67MHz and from 975MHz to 1,300MHz an optimum of high clock frequency and low phase noise Frequency programming resolution is 218Hz and better performance. The device accepts 2.5V or 3.3V supply and is One 2.5V, 3.3V LVDS clock output packaged in a small, lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm Output enable control (positive polarity), LVCMOS/LVTTL x 1.55mm package. compatible The device can be factory programmed to any in the range from RMS phase jitter 231.25MHz (12kHz - 20MHz): 15.476MHz to 866.67MHz and from 975MHz to 1,300MHz and 0.48ps (typical), integer PLL feedback configuration supports a very high degree of frequency precision of 218Hz or RMS phase jitter 231.25MHz (1kHz - 40MHz): better. The extended temperature range supports wireless 0.50ps (typical), integer PLL feedback configuration infrastructure, telecommunication and networking end equipment 2.5V or 3.3V supply requirements. -40C to 85C ambient operating temperature Available in a lead-free (RoHS 6) 6-pin ceramic package Block Diagram Pin Assignment OE 1 6 V DD PFD FemtoClock NG Q P OSC & VCO N DNU 2 5 nQ nQ LPF GND 3 4 Q f XTAL MINT, MFRAC IDT8N4S270 2 6-lead ceramic 5mm x 7mm x 1.55mm package body 25 7 CD Package Configuration Register (ROM) Top View Pullup OE IDT8N4S270CCD REVISION A AUGUST 31, 2012 1 2012 Integrated Device Technology, Inc.IDT8N4S270 Data Sheet LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR Pin Description and Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1 OE Input Pullup Output enable pin. See Table 3A for function. LVCMOS/LVTTL interface levels. 2 DNU Do not use (factory use only). 3 GND Power Power supply ground. 4, 5 Output Differential clock output pair. LVDS interface levels. Q, nQ 6 V Power Power supply pin. DD NOTE: Pullup refers to an internal input resistor. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 5.5 pF IN R Input Pullup Resistor 50 k PULLUP Function Tables Table 3A. OE Configuration Input OE Output Enable 0 Outputs Q, nQ are in high-impedance state 1 (default) Outputs Q, nQ are enabled NOTE: OE is an asynchronous control. IDT8N4S270CCD REVISION A AUGUST 31, 2012 2 2012 Integrated Device Technology, Inc.