1:12 LVDS 1.8V / 2.5V Fanout Buffer 8P34S1212 for 1PPS and High-Speed Clocks Datasheet Description Features The 8P34S1212 is a high-performance differential LVDS fanout 12 low skew, low additive jitter LVDS output pairs buffer. The device is designed for the fanout of 1PPS signals or Two selectable, differential clock input pairs high-frequency, very low additive phase-noise clock and data Differential CLK0, CLK1 pairs can accept the following signals. The 8P34S1212 is characterized to operate from a differential input levels: LVDS, CML 1.8V or 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8P34S1212 ideal for Maximum input clock frequency: 1.5GHz (maximum) those clock distribution applications that demand well-defined LVCMOS/LVTTL interface levels for the control input select pin performance and repeatability. Output skew: 10ps (typical) Two selectable differential inputs and 12 low skew outputs are Propagation delay: 400ps (maximum) available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The Low propagation delay variation across temperature for 1PPS applications device is optimized for low power consumption and low additive phase noise. Low additive phase jitter, RMS f = 156.25MHz, V = 1V, REF PP 12kHz 20MHz: 34fs (typical) Maximum device current consumption (I ): 185mA typ at 1.8V DD or 200mA typ at 2.5V Full 1.8V or 2.5V supply voltage Lead-free (RoHS 6), 40-Lead VFQFPN packaging -40C to +85C ambient operating temperature Supports case temperature up to +105C Supports PCI Express Gen 1-5 Block Diagram Pin Assignment Q0 nQ0 30 29 28 27 26 25 24 23 22 21 Q1 nQ1 V 31 20 V DD DD Q2 Q8 32 19 nQ3 8P34S1212 nQ2 nQ8 33 18 Q3 V DD 40-Lead VFQFPN Q3 Q9 34 17 nQ2 nQ3 6.0mm x 6.0mm x 0.90mm CLK0 35 16 nQ9 Q2 package body Q4 nCLK0 nQ4 36 15 Q10 nQ1 4.65mm x 4.65mm ePad Size 37 14 Q5 nQ10 Q1 NL Package f nQ5 REF 38 13 Q11 nQ0 Top View 39 12 Q6 nQ11 Q0 V DD nQ6 40 11 V V DD DD CLK1 Q7 1 2 3 4 5 6 7 8 9 10 nQ7 nCLK1 Q8 nQ8 Q9 SEL nQ9 Q10 nQ10 V V REF REF Q11 nQ11 2021 Renesas Electronics Corporation 1 August 30, 2021 SEL GND CLK1 nQ7 nCLK1 Q7 nc nQ6 V Q6 DD V nQ5 DD VREF Q5 nCLK0 nQ4 CLK0 Q4 nc GND8P34S1212 Datasheet Pin Descriptions and Characteristics a Table 1. Pin Descriptions Number Name Type Description Reference select control. See Table 3 for function. 1 SEL Input Pulldown LVCMOS/LVTTL interface levels. 2 CLK1 Input Pulldown Non-inverting differential clock/data input. Pulldown/ 3 nCLK1 Input Inverting differential clock/data input. Pullup 4, 10 nc Unused Do not connect. 5, 6, 11, 20, V Power Power supply pins. DD 31, 40 Bias voltage reference. Provides an input bias voltage for the CLKx, 7 V nCLKx input pairs in AC-coupled applications. Refer to Figures 2B and REF 2C for applicable AC-coupled input interfaces. Pulldown/ 8 nCLK0 Input Inverting differential clock/data input. Pullup 9 CLK0 Input Pulldown Non-inverting differential clock/data input. 12, 13 Q0, nQ0 Output Differential output pair 0. LVDS interface levels. 14, 15 Q1, nQ1 Output Differential output pair 1. LVDS interface levels. 16, 17 Q2, nQ2 Output Differential output pair 2. LVDS interface levels. 18, 19 Q3, nQ3 Output Differential output pair 3. LVDS interface levels. 21, 30 GND Power Power supply ground. 22, 23 Q4, nQ4 Output Differential output pair 4. LVDS interface levels. 24, 25 Q5, nQ5 Output Differential output pair 5. LVDS interface levels. 26, 27 Q6, nQ6 Output Differential output pair 6. LVDS interface levels. 28, 29 Q7, nQ7 Output Differential output pair 7. LVDS interface levels. 32, 33 Q8, nQ8 Output Differential output pair 8. LVDS interface levels. 34, 35 Q9, nQ9 Output Differential output pair 9. LVDS interface levels. 36, 37 Q10, nQ10 Output Differential output pair 10. LVDS interface levels. 38, 39 Q11, nQ11 Output Differential output pair 11. LVDS interface levels. a Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 2 pF IN R Input Pulldown Resistor 51 k PULLDOWN R Input Pullup Resistor 51 k PULLUP a Table 3. SEL Input Function Table Input SEL Operation 0 (Default) CLK0, nCLK0 is the selected differential clock input. 1 CLK1, nCLK1 is the selected differential clock input. a SEL is an asynchronous control. 2021 Renesas Electronics Corporation 2 August 30, 2021