1:4 LVDS 1.8V / 2.5V Fanout Buffer 8P34S1204 Datasheet for 1PPS and High-Speed Clocks Description Features The 8P34S1204 is a high-performance differential LVDS fanout Four low skew, low additive jitter LVDS output pairs buffer. The device is designed for the fanout of 1PPS signals or Two selectable, differential clock input pairs high-frequency, very low additive phase-noise clock and data Differential CLK, nCLK pairs can accept the following signals. The 8P34S1204 is characterized to operate from a differential input levels: LVDS, CML 1.8V or 2.5V power supply. Guaranteed low output-to-output and part-to-part skew characteristics make the 8P34S1204 Maximum input clock frequency: 1.5GHz ideal for those clock distribution applications demanding LVCMOS/LVTTL interface levels for the control input select well-defined performance and repeatability. Two selectable differential inputs and four low skew outputs are available. The Output skew: 10ps (typical) integrated bias voltage reference enables easy interfacing of Propagation delay: 400ps (maximum) single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase Low propagation delay variation across temperature for 1PPS noise. applications Low additive phase jitter, RMS f = 156.25MHz, REF 10kHz20MHz: 34fs (typical) Device current consumption (I ): DD 65mA typical: 1.8V 75mA typical: 2.5V Full 1.8V or 2.5V supply voltage Lead-free (RoHS 6), 16-Lead VFQFPN package -40C to +85C ambient operating temperature Supports case temperature up to +105C Supports PCI Express Gen 1-5 Block Diagram Pin Assignment V DD 12 11 10 9 Pulldown Q0 CLK0 Q2 13 8 V nQ0 REF Pullup/Pulldown nCLK0 nQ2 14 7 nCLK0 Q1 Q3 15 6 CLK0 nQ1 0 f REF nQ3 16 5 V DD 1 Q2 V DD 1 2 3 4 nQ2 Pulldown CLK1 Q3 Pullup/Pulldown nCLK1 nQ3 8P34S1204 16-VFQFPN 3 x 3 x 0.9 mm package body Pulldown SEL 1.7 x 1.7 mm ePad Size NLG Package Voltage V REF Reference Top View 2021 Renesas Electronics Corporation 1 August 13, 2021 GND nQ1 SEL Q1 CLK1 nQ0 nCLK1 Q08P34S1204 Datasheet Pin Description and Pin Characteristic Tables a Table 1. Pin Descriptions Number Name Type Description 1 GND Power Power supply ground. Reference select control pin. See Table 3 for function. LVCMOS/LVTTL 2 SEL Input Pulldown interface levels. 3 CLK1 Input Pulldown Non-inverting differential clock/data input. Pullup/ 4 nCLK1 Input Inverting differential clock/data input. V /2 default when left floating. DD Pulldown 5 V Power Power supply pin. DD 6 CLK0 Input Pulldown Non-inverting differential clock/data input. Pullup/ 7 nCLK0 Input Inverting differential clock/data input. V /2 default when left floating. DD Pulldown Bias voltage reference. Provides an input bias voltage for the 8 V Output CLK 0:1 , nCLK 0:1 input pairs in AC-coupled applications. Refer to REF Figures 2B and 2C for applicable AC-coupled input interfaces. 9, 10 Q0, nQ0 Output Differential output pair 0. LVDS interface levels. 11, 12 Q1, nQ1 Output Differential output pair 1. LVDS interface levels. 13, 14 Q2, nQ2 Output Differential output pair 2. LVDS interface levels. 15, 16 Q3, nQ3 Output Differential output pair 3. LVDS interface levels. a Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 2 pF IN R Input Pulldown Resistor 51 k PULLDOWN R Input Pullup Resistor 51 k PULLUP a Table 3. SEL Input Function Table Input SEL Operation 0 (default) CLK0, nCLK0 is the selected differential clock input. 1 CLK1, nCLK1 is the selected differential clock input. a SEL is an asynchronous control. 2021 Renesas Electronics Corporation 2 August 13, 2021