8N4SV75LC-0161CDI Renesas

LVDS Frequency-Programmable VCXO IDT8N4SV75 DATA SHEET General Description Features The IDT8N4SV75 is a LVDS Frequency-Programmable VCXO with Fourth generation FemtoClock NG technology very flexible frequency and pull-range programming capabilities. The Programmable clock output frequency from 15.476MHz to device uses IDTs fourth generation FemtoClock NG technology for 866.67MHz and from 975MHz to 1,300MHz an optimum of high clock frequency and low phase noise Frequency programming resolution is 218Hz and better performance. The device accepts 2.5V or 3.3V supply and is Factory-programmable VCXO pull range and control voltage packaged in a small, lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm polarity x 1.55mm package. Absolute pull-range (APR) programmable from 4.5 to The device can be factory-programmed to any frequency in the 754.5ppm range of 15.476MHz to 866.67MHz and from 975MHz to 1,300MHz One 2.5V / 3.3V LVDS clock output to the very high degree of frequency precision of 218Hz or better. Output enable control input, LVCMOS/LVTTL compatible The extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements. RMS phase jitter 156.25MHz (12kHz - 20MHz): 0.53ps (typical) 2.5V or 3.3V supply voltage -40C to 85C ambient operating temperature Lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm x 1.55mm package Block Diagram Pin Assignment VC 1 6 V DD PFD FemtoClock NG Q P OE 2 5 nQ OSC & N VCO nQ LPF 1950-2600MHz GND 3 4 Q 114.285 MHz IDT8N4SV75 2 MINT, MFRAC 6-lead ceramic 5mm x 7mm x 1.55mm package body A/D VC CD Package 7 25 7 Top View Configuration Register (ROM) (Frequency, APR, Polarity) Pullup OE IDT8N4SV75CCD REVISION B NOVEMBER 6, 2013 1 2013 Integrated Device Technology, Inc.IDT8N4SV75 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO Pin Description and Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1 VC Input VCXO Control Voltage input. 2 OE Input Pullup Output enable pin. See Table 3A for function. LVCMOS/LVTTL interface levels. 3 GND Power Power supply ground. 4, 5 Output Differential clock output pair. LVDS interface levels. Q, nQ 6 Power Power supply pin. V DD NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units OE 5.5 pF C Input Capacitance IN VC 10 pF R Input Pullup Resistor 50 k PULLUP IDT8N4SV75CCD REVISION B NOVEMBER 6, 2013 2 2013 Integrated Device Technology, Inc.