Dual 1:2 LVDS Output 1.8V / 2.5V 8P34S2102 Fanout Buffer Datasheet Description Features Dual 1:2 low skew, low additive jitter LVDS fanout buffers The 8P34S2102 is a high-performance, low-power, differential dual 1:2 LVDS output, 1.8V/2.5V fanout buffer. The device is Matched AC characteristics across both channels designed for the fanout of high-frequency, very low additive High isolation between channels phase-noise clock and data signals. Both differential CLKA, nCLKA and CLKB, nCLKB inputs Two independent buffer channels are available. Each channel has accept LVDS, LVPECL and single-ended LVCMOS levels two low-skew outputs. High isolation between channels minimizes Maximum input clock frequency: 2GHz noise coupling. AC characteristics such as propagation delay are Output amplitudes: 350mV, 500mV (selectable) matched between channels. Guaranteed output-to-output and Output bank skew: 8ps typical part-to-part skew characteristics make the 8P34S2102 ideal for those clock distribution applications demanding well-defined Output skew: 10ps typical performance and repeatability. Low additive phase jitter, RMS: 45fs typical (f = 156.25MHz, 12kHz 20MHz) REF The device is characterized to operate from a 1.8V or a 2.5V Full 1.8V and 2.5V supply voltage mode power supply. The integrated bias voltage references enable easy interfacing of AC-coupled signals to the device inputs. Low device current consumption (I ): DD 76mA typical: 1.8V 80mA typical: 2.5V Lead-free (RoHS 6), 16-lead VFQFPN packaging -40C to +85C ambient operating temperature Supports case temperature up to +105C Block Diagram VDD 51k QA0 nQA0 CLKA nCLKA QA1 nQA1 51k 51k Voltage VREF Reference VDD 51k QB0 nQB0 CLKB nCLKB QB1 VDD nQB1 51k 51k 51k SELA 8P34S2102 transistor count: 293 2021 Renesas Electronics Corporation 1 May 10, 20218P34S2102 Datasheet Pin Assignments Figure 1. Pin Assignments for 3 3 mm VFQFPN Package Top View 11 10 9 12 QB0 13 8 VREF 7 nQB0 14 nCLKA 8P34S2102 6 CLKA QB1 15 8XXXXXX 5 V nQB1 16 DD 1 2 34 Pin Descriptions Table 1. Pin Descriptions a Number Name Type Description 1 GND Power Power supply ground. 2 SELA Input (PU) Control input. Output amplitude select. 3 CLKB Input (PD) Non-inverting differential clock/data input for channel B. 4 nCLKB Input (PD/PU) Inverting differential clock/data input for channel B. 5V Power Power supply pin. DD 6 CLKA Input (PD) Non-inverting differential clock/data input for channel A. 7 nCLKA Input (PD/PU) Inverting differential clock/data input for channel A. 8 VREF Output Bias voltage reference for CLKA, nCLKA and CLKB, nCLKB input pairs. 9 QA0 Output Differential output A0. LVDS interface levels. 10 nQA0 Output Differential output A0. LVDS interface levels. 11 QA1 Output Differential output A1. LVDS interface levels. 12 nQA1 Output Differential output A1. LVDS interface levels. 13 QB0 Output Differential output B0. LVDS interface levels. 14 nQB0 Output Differential output B0. LVDS interface levels. 15 QB1 Output Differential output B1. LVDS interface levels. 16 nQB1 Output Differential output B1. LVDS interface levels. ePad GND EPAD Power Exposed pad of package. Connect to ground. a Pull-up (PU) and pull-down (PD) resistors are indicated in parentheses. Pull-up and pull-down refers to internal input resistors. See Table 4, DC Input Characteristics, for typical values. 2021 Renesas Electronics Corporation 2 May 10, 2021 GND nQA1 SELA QA1 CLKB nQA0 nCLKB QA0