Dual 1:8 LVDS Output 1.8V / 2.5V 8P34S2108 Fanout Buffer Datasheet Description Features Dual 1:8 low skew, low additive jitter LVDS fanout buffers The 8P34S2108 is a high-performance, low-power, differential dual 1:8 LVDS output 1.8V/2.5V fanout buffer. The device is Matched AC characteristics across both channels designed for the fanout of high-frequency, very low additive High isolation between channels phase-noise clock and data signals. Two independent buffer Both differential CLKA, nCLKA and CLKB, nCLKB inputs channels are available, each channel has two low skew outputs. accept LVDS, LVPECL and single-ended LVCMOS levels High isolation between channels minimizes noise coupling. AC Maximum input clock frequency: 2GHz characteristics such as propagation delay are matched between channels. Guaranteed output-to-output and part-to-part skew Output amplitudes: 350mV, 500mV (selectable) characteristics make the 8P34S2108 ideal for those clock Output bank skew: 10ps typical distribution applications demanding well-defined performance and Output skew: 20ps typical repeatability. The device is characterized to operate from a 1.8V Low additive phase jitter, RMS: 45fs typical or 2.5V power supply. The integrated bias voltage references (f = 156.25MHz, 12kHz 20MHz) enable easy interfacing AC-coupled signals to the device inputs. REF Full 1.8V and 2.5V supply voltage mode Block Diagram Low device current consumption (I ): DD QA0 280mA typical: 1.8V nQA0 290mA typical: 2.5V QA1 nQA1 Lead-free (RoHS 6), 48-lead VFQFPN packaging QA2 -40C to +85C ambient operating temperature VDDA nQA2 Supports case temperature up to +105C 51k QA3 nQA3 CLKA nCLKA QA4 nQA4 51k 51k QA5 nQA5 QA6 VDDA Voltage nQA6 VREFA Reference A 51k QA7 nQA7 SELAA QB0 nQB0 QB1 nQB1 QB2 VDDB nQB2 51k QB3 nQB3 CLKB nCLKB QB4 nQB4 51k 51k QB5 nQB5 Voltage VREFB VDDB QB6 Reference B nQB6 51k QB7 nQB7 SELAB 8P34S2108 transistor count: 1113 2021 Renesas Electronics Corporation 1 R31DS0018EU0700 May 10, 20218P34S2108 Datasheet Pin Assignments Figure 1. Pin Assignments for 7 7 mm 48-VFQFPN Package Top View 36 35 34 33 32 31 30 29 28 27 26 25 V 37 24 V DDQA DDQB 38 23 nQA4 QB3 22 nQB3 39 QA4 40 21 nQA3 QB4 nQB4 41 20 QA3 19 nQA2 QB5 42 8P34S2108 nQB5 43 18 QA2 nQA1 QB6 44 17 16 QA1 nQB6 45 46 15 QB7 nQA0 nQB7 47 14 QA0 48 13 V V DDQB DDQA 12 34 56 7 8 9 101112 Pin Descriptions a Table 1. Pin Descriptions Number Name Type Description 1 GND Power Power supply ground. 2 SELAB Input PU Control input. Output amplitude select for channel B. 3 CLKB Input PD Non-inverting differential clock/data input for channel B. 4 nCLKB Input PD/PU Inverting differential clock/data input for channel B. 5 VREFB Output Bias voltage reference for the CLKB, nCLKB input pairs. 6V Power Power supply pins for the core and inputs of channel B. DDB 7V Power Power supply pins for the core and inputs of channel A. DDA 8 VREFA Output Bias voltage reference for the CLKA, nCLKA input pairs. 9 nCLKA Input PD/PU Inverting differential clock/data input. 10 CLKA Input PD Non-inverting differential clock/data input. 11 SELAA Input PU Control input: Output amplitude select for channel A. 12 GND Power Power supply ground. 13 V Power Power supply pin for the channel A outputs QA 0:7 . DDQA 14 QA0 Output Differential output pair A0. LVDS interface levels. 15 nQA0 Output Differential output pair A0. LVDS interface levels. 2021 Renesas Electronics Corporation 2 R31DS0018EU0700 May 10, 2021 GND nQB2 QB2 SELAB CLKB nQB1 nCLKB QB1 VREFB nQB0 V QB0 DDB V nQA7 DDA VREFA QA7 nCLKA nQA6 CLKA QA6 SELAA nQA5 GND QA5