8P34S1106I 1:6 LVDS Output 1.8V Fanout Buffer Datasheet Description Features Six low skew, low additive jitter LVDS output pairs The 8P34S1106I is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, One differential clock input pair very low additive phase-noise clock and data signals. The Differential CLK, nCLK pair can accept the following differential 8P34S1106I is characterized to operate from a 1.8V power input levels: LVDS, CML supply. Maximum input clock frequency: 1.2GHz (maximum) Guaranteed output-to-output and part-to-part skew Output skew: 20ps (typical) characteristics make the 8P34S1106I ideal for those clock Propagation delay: 290ps (typical) distribution applications demanding well-defined performance Low additive phase jitter, RMS f = 156.25MHz, V = 1V, REF PP and repeatability. One differential input and six low skew 12kHz- 20MHz: 39fs (typical) outputs are available. The integrated bias voltage reference Full 1.8V supply voltage enables easy interfacing of single-ended signals to the differential device input. The device is optimized for low power Lead-free (RoHS 6), 20-Lead VFQFN packaging consumption and low additive phase jitter. -40C to 85C ambient operating temperature Block Diagram Pin Assignment Q0 V DD 15 14 13 12 11 nQ0 Q3 16 10 nQ0 CLK nQ3 17 9 Q0 Q1 nCLK Q4 18 8 V Top View REF nQ1 nQ4 19 7 nCLK VDD 20 6 CLK V Q2 REF 1 2 3 4 5 nQ2 8P34S1106I Q3 20-VFQFPN 4 x 4 x 0.9 mm package body 2.1 x 2.1 mm ePad Size NLG Package Top View 2021 Renesas Electronics Corporation 1 R31DS0030EU0500 May 10, 2021 GND nQ2 Q5 Q2 nQ5 nQ1 nc Q1 V VDD DD8P34S1106I Datasheet Pin Description and Pin Characteristic Tables a Table 1. Pin Descriptions Number Name Type Description 1 GND Power Power supply ground. 2, 3 Q5, nQ5 Output Differential output pair 5. LVDS interface levels. 4 NC Unused Do not connect. 5, 11, 20 V Power Power supply pins. DD 6 CLK Input Pulldown Non-inverting differential clock/data input. Pulldown/ 7 nCLK Input Inverting differential clock/data input. Pullup Bias voltage reference. Provides an input bias voltage for the CLK, nCLK 8 V input pair in AC-coupled applications. Refer to Figures 2B and 2C for REF applicable AC-coupled input interfaces. 9, 10 Q0, nQ0 Output Differential output pair 0. LVDS interface levels. 12, 13 Q1, nQ1 Output Differential output pair 1. LVDS interface levels. 14, 15 Q2, nQ2 Output Differential output pair 2. LVDS interface levels. 16, 17 Q3, nQ3 Output Differential output pair 3. LVDS interface levels. 18, 19 Q4, nQ4 Output Differential output pair 4. LVDS interface levels. a Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 2 pF IN R Input Pulldown Resistor 51 k PULLDOWN R Input Pullup Resistor 51 k PULLUP 2021 Renesas Electronics Corporation 2 R31DS0030EU0500 May 10, 2021