1:8 LVDS 1.8V / 2.5V Fanout Buffer 8P34S1208 for 1PPS and High-Speed Clocks Datasheet Description Features The 8P34S1208 is a high-performance differential LVDS fanout Eight low skew, low additive jitter LVDS output pairs buffer. The device is designed for the fanout of 1PPS signals or Two selectable, differential clock input pairs high-frequency, very low additive phase-noise clock and data Differential CLK, nCLK pairs can accept the following signals. differential input levels: LVDS, CML The 8P34S1208 is characterized to operate from a 1.8V or 2.5V Maximum input clock frequency: 1.5GHz power supply. Guaranteed output-to-output and part-to-part LVCMOS/LVTTL interface levels for the control input select pin skew characteristics make the 8P34S1208 ideal for those clock Output skew: 20ps (typical) distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and eight Propagation delay: 400ps (maximum) low skew outputs are available. The integrated bias voltage Low propagation delay variation across temperature for 1PPS reference enables easy interfacing of single-ended signals to applications the device inputs. The device is optimized for low power Low additive phase jitter, RMS f = 156.25MHz, V = 1V, consumption and low additive phase noise. REF PP 12kHz20MHz: 34fs (typical) Device current consumption (I ): DD 120mA typical: 1.8V 132mA typical: 2.5V Full 1.8V or 2.5V supply voltage Lead-free (RoHS 6), 28-Lead VFQFPN packaging -40C to +85C ambient operating temperature Supports case temperature up to +105C Supports PCI Express Gen 1-5 Block Diagram Pin Assignment Q0 21 20 19 18 17 16 15 Voltage nQ0 V REF0 Reference Q4 22 8P34S1208 14 GND V DD 28-lead VFQFPN nQ4 23 13 nQ0 Q1 5.0 x 5.0 x 0.75 mm Q5 24 12 Q0 nQ1 package body 25 11 nQ5 V REF0 3.25 x 3.25 mm ePad Size Q6 26 10 nCLK0 CLK0 Q2 NBG Package 27 9 f nQ6 CLK0 REF nCLK0 nQ2 Top View V 28 8 V DD DD V DD 1 2 3 4 5 6 7 Q3 nQ3 Q4 nQ4 CLK1 Voltage Reference nCLK1 2021 Renesas Electronics Corporation 1 August 30, 2021 GND nQ3 Q7 Q3 nQ7 nQ2 SEL Q2 CLK1 nQ1 nCLK1 Q1 V V REF1 DD8P34S1208 Datasheet Pin Description and Pin Characteristic Tables a Table 1. Pin Descriptions Number Name Type Description 1, 14 GND Power Power supply pin. 2, 3 Q7, nQ7 Output Differential output pair 7. LVDS interface levels. Reference select control pin. See Table 3 for function. LVCMOS/LVTTL 4 SEL Input Pulldown interface levels. 5 CLK1 Input Pulldown Non-inverting differential clock/data input 1. Pullup/ 6 nCLK1 Input Inverting differential clock/data input 1. V /2 default when left floating. DD Pulldown Bias voltage reference. Provides an input bias voltage for the CLK1, nCLK1 7 V Output input pair in AC-coupled applications. Refer to Figures 2B and 2C for REF1 applicable AC-coupled input interfaces. 8, 15, 28 V Power Power supply pin. DD 9 CLK0 Input Pulldown Non-inverting differential clock/data input 0. Pullup/ 10 nCLK0 Input Inverting differential clock/data input 0. V /2 default when left floating. DD Pulldown Bias voltage reference. Provides an input bias voltage for the CLK0, nCLK0 11 V Output input pair in AC-coupled applications. Refer to Figures 2B and 2C for REF0 applicable AC-coupled input interfaces. 12, 13 Q0, nQ0 Output Differential output pair 0. LVDS interface levels. 16, 17 Q1, nQ1 Output Differential output pair 1. LVDS interface levels. 18, 19 Q2, nQ2 Output Differential output pair 2. LVDS interface levels. 20, 21 Q3, nQ3 Output Differential output pair 3. LVDS interface levels. 22, 23 Q4, nQ4 Output Differential output pair 4. LVDS interface levels. 24, 25 Q5, nQ5 Output Differential output pair 5. LVDS interface levels. 26, 27 Q6, nQ6 Output Differential output pair 6. LVDS interface levels. a Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 2 pF IN R Input Pulldown Resistor 51 k PULLDOWN R Input Pullup Resistor 51 k PULLUP a Table 3. SEL Input Function Table Input SEL Operation 0 CLK0, nCLK0 is the selected differential clock input. 1 CLK1, nCLK1 is the selected differential clock input. a SEL is an asynchronous control. 2021 Renesas Electronics Corporation 2 August 30, 2021