Dual 1:4 LVDS Output 1.8V / 2.5V 8P34S2104 Fanout Buffer Datasheet Description Features Dual 1:4 low skew, low additive jitter LVDS fanout buffers The 8P34S2104 is a high-performance, low-power, differential dual 1:4 LVDS Output 1.8V/2.5V fanout buffer. The device is Matched AC characteristics across both channels designed for the fanout of high-frequency, very low additive High isolation between channels phase-noise clock and data signals. Two independent buffer Both differential CLKA, nCLKA and CLKB, nCLKB inputs channels are available. Each channel has four low-skew outputs. accept LVDS, LVPECL, and single-ended LVCMOS levels High isolation between channels minimizes noise coupling. AC Maximum input clock frequency: 2GHz characteristics such as propagation delay are matched between channels. Guaranteed output-to-output and part-to-part skew Output amplitudes: 350mV, 500mV (selectable) characteristics make the 8P34S2104 ideal for those clock Output bank skew: 8ps typical distribution applications demanding well-defined performance and Output skew: 10ps typical repeatability. The device is characterized to operate from a 1.8V Low additive phase jitter, RMS: 45fs typical or a 2.5V power supply. The integrated bias voltage references (f = 156.25MHz, 12kHz 20MHz) enable easy interfacing of AC-coupled signals to the device REF inputs. Full 1.8V and 2.5V supply voltage mode Low device current consumption (I ): DD 135mA typical: 1.8V 145mA typical: 2.5V Lead-free (RoHS 6), 28-VFQFPN packaging -40C to +85C ambient operating temperature Supports case temperature up to +105C Block Diagram QA0 VDDQA nQA0 51k QA1 nQA1 CLKA nCLKA QA2 nQA2 51k 51k QA3 nQA3 Voltage VREFA Reference A QB0 VDDQB nQB0 QB1 51k nQB1 CLKB nCLKB QB2 nQB2 51k 51k VDDQB QB3 nQB3 51k Voltage VREFB Reference B SELA 8P34S2104 transistor count: 2021 Renesas Electronics Corporation 1 May 10, 20218P34S2104 Datasheet Pin Assignments Figure 1. Pin Assignments for 5 5 mm 28-VFQFPN Package Top View 21 20 19 18 17 16 15 QB0 22 14 GND nQB0 23 13 nQA0 QB1 24 12 QA0 nQB1 25 VREFA 8P34S2104 11 QB2 26 10 nCLKA 9 CLKA nQB2 27 V 28 8 V DDQA DDQB 1 23 4 5 6 7 Pin Descriptions Table 1. Pin Descriptions a Number Name Type Description 1 GND Power Power supply ground. 2 QB3 Output Differential output B3. LVDS interface levels. 3 nQB3 Output Differential output B3. LVDS interface levels. 4 SELA Input (PU) Control input. Output amplitude select. 5 CLKB Input (PD) Non-inverting differential clock/data input for channel B. 6 nCLKB Input (PD/PU) Inverting differential clock/data input for channel B. 7 VREFB Output Bias voltage reference for CLKB, nCLKB input pairs. 8V Power Power supply pin for the channel A core input and QA 0:3 outputs. DDQA 9 CLKA Input (PD) Non-inverting differential clock/data input for channel A. 10 nCLKA Input (PD/PU) Inverting differential clock/data input for channel A. 11 VREFA Output Bias voltage reference for CLKA, nCLKA input pairs. 12 QA0 Output Differential output pair A0. LVDS interface levels. 13 nQA0 Output Differential output pair A0. LVDS interface levels. 14 GND Power Power supply ground. 15 V Power Power supply pin for the channel A core input and QA 0:3 outputs. DDQA 16 QA1 Output Differential output pair A1. LVDS interface levels. 17 nQA1 Output Differential output pair A1. LVDS interface levels. 2021 Renesas Electronics Corporation 2 May 10, 2021 GND nQA3 QB3 QA3 nQB3 nQA2 SELA QA2 CLKB nQA1 nCLKB QA1 VREFB V DDQA