Dual 1:6 LVDS Output 1.8V / 2.5V 8P34S2106 Fanout Buffer Datasheet Description Features Dual 1:6 low skew, low additive jitter LVDS fanout buffers The 8P34S2106 is a high-performance, low-power, differential dual 1:6 LVDS output 1.8V/2.5V fanout buffer. The device is Matched AC characteristics across both channels designed for the fanout of high-frequency, very low additive High isolation between channels phase-noise clock and data signals. Two independent buffer Low power consumption channels are available, each channel has six low skew outputs. Both differential CLKA, nCLKA and CLKB, nCLKB inputs High isolation between channels minimizes noise coupling. AC accept LVDS, LVPECL and single-ended LVCMOS levels characteristics such as propagation delay are matched between channels. Maximum input clock frequency: 2GHz Output amplitudes: 350mV, 500mV (selectable) Guaranteed output-to-output and part-to-part skew characteristics make the 8P34S2106 ideal for those clock distribution Output bank skew: 10ps typical applications demanding well-defined performance and Output skew: 20ps typical repeatability. The device is characterized to operate from a Low additive phase jitter, RMS: 45fs typical 1.8V/2.5V power supply. The integrated bias voltage references (f = 156.25MHz, 12kHz 20MHz) REF enable easy interfacing of AC-coupled signals to the device Full 1.8V and 2.5V supply voltage mode inputs. Device current consumption (I ): DD 210mA typical: 1.8V Block Diagram 230mA typical: 2.5V QA0 Lead-free (RoHS 6) packaging: nQA0 40-VFQFPN, 6 x 6 x 0.9 mm QA1 VDDA 48-WL-CSP, 3.59 x 3.04 x 0.6 mm nQA1 -40C to 85C ambient operating temperature 51k QA2 Supports case temperature up to 105C nQA2 CLKA nCLKA QA3 nQA3 51k 51k QA4 VDDA nQA4 Voltage VREFA 51k Reference A QA5 nQA5 SELAA QB0 nQB0 QB1 VDDB nQB1 51k QB2 nQB2 CLKB nCLKB QB3 nQB3 51k 51k QB4 VDDB nQB4 Voltage VREFB 51k Reference B QB5 nQB5 SELAB 2021 Renesas Electronics Corporation 1 May 10, 20218P34S2106 Datasheet Pin Assignments for 40-VFQFPN Package Figure 1. Pin Assignments for 40-VFQFPN, 6 x 6 mm Package Top View 30 29 28 27 26 25 24 23 22 21 31 20 V V DDQB DDQA 19 QB2 32 nQA3 18 33 QA3 nQB2 17 nQA2 34 QB3 16 QA2 35 nQB3 8P34S2106 15 nQA1 36 QB4 14 QA1 37 nQB4 13 nQA0 38 QB5 12 QA0 39 nQB5 11 V DDQA 40 V DDQB 12 3 4 5 6 7 8 9 10 Pin Descriptions for 40-VFQFPN Package a Table 1. 40-VFQFPN Pin Descriptions Number Name Type Description 1 SELAB Input PU Control input. Output amplitude select for channel B. 2 CLKB Input PD Non-inverting differential clock/data input for channel B. 3 nCLKB Input PD/PU Inverting differential clock/data input for channel B. 4 VREFB Output Bias voltage reference for the CLKB, nCLKB input pairs. 5V Power Power supply pin for the core and inputs of channel B. DDB 6V Power Power supply pin for the core and inputs of channel A. DDA 7 VREFA Output Bias voltage reference for the CLKA, nCLKA input pairs. 8 nCLKA Input PD/PU Inverting differential clock/data input for channel A. 9 CLKA Input PD Non-inverting differential clock/data input for channel A. 10 SELAA Input PU Control input. Output amplitude select for channel A. 11 V Power Power supply pin for the channel A outputs QA 0:5 DDQA 12 QA0 Output Differential output pair A0. LVDS interface levels. 13 nQA0 Output Differential output pair A0. LVDS interface levels. 14 QA1 Output Differential output pair A1. LVDS interface levels. 15 nQA1 Output Differential output pair A1. LVDS interface levels. 2021 Renesas Electronics Corporation 2 May 10, 2021 SELAB GND nQB1 CLKB nCLKB QB1 nQB0 VREFB V QB0 DDB V nQA5 DDA VREFA QA5 nCLKA nQA4 CLKA QA4 SELAA GND