Low Additive Jitter 2:8 Buffer with 8P391208 Universal Differential Outputs Datasheet Description Features Two differential inputs support LVPECL, LVDS, HCSL or LVCMOS The 8P391208 is intended to take 1 or 2 reference clocks, select between them, using a pin selection and generate up to 8 outputs reference clocks that are the same as the reference frequency. Accepts input frequencies ranging from 1PPS (1Hz) to 700MHz (up to 1GHz when configured into HCSL output mode at 3.3V) 8P391208 supports two output banks, each with its own power Select which of the two input clocks is to be used as the reference supply. All outputs in one bank would generate the same output clock for which bank via pin selection frequency, and each bank can be individually controlled for output type or output enable. Generates 8 differential outputs Differential outputs selectable as LVPECL, LVDS, CML or HCSL The device can operate over the -40C to +85C temperature range. CML mode supports two different voltage swings Differential outputs support frequencies from 1PPS to 700MHz (up to 1GHz when configured into HCSL output mode at 3.3V) Outputs arranged in 2 banks of 4 outputs each Each bank supports a separate power supply of 3.3V, 2.5V or 1.8V Controlled by 3-level input pins Input mux selection control pin Control inputs are 3.3V-tolerant for all core voltages Output noise floor of -153dBc/Hz 156.25MHz Core voltage supply of 3.3V, 2.5V or 1.8V -40C to +85C ambient operating temperature Lead-free (RoHS 6) packaging Block Diagram QA0 nQ A0 QA1 nQ A1 CL K SEL QA2 nQ A2 QA3 CL K0 nQ A3 nCLK0 QB0 nQ B0 CL K1 nCLK1 QB1 nQ B1 QB2 nQ B2 QB3 nQ B3 IO A 2 Logic IO B 2 2020 Renesas Electronics Corporation 1 November 25, 20208P391208 Datasheet Pin Assignments Figure 1: Pin Assignments for 5mm x 5mm 32-pin VFQFN Package 32 31 30 29 28 27 26 25 1 24 IOB1 IOA1 2 23 QB0 QA0 3 22 nQB0 nQA0 4 21 QA1 QB1 5 nQA1 20 nQB1 6 V 19 V CCOB CCOA 7 QA2 18 QB2 8 nQA2 17 nQB2 9 10 11 12 13 14 15 16 Pin Description and Characteristic Tables Table 1: Pin Description 1 Number Name Type Description Pullup / 1 IOA1 Input Controls output functions for Bank A. 3-level input. Pulldown Positive differential clock output. Included in Bank A. 2 QA0 Output Refer to Output Drivers section for more details. Negative differential clock output. Included in Bank A. 3 nQA0 Output Refer to Output Drivers section for more details. Positive differential clock output. Included in Bank A. 4 QA1 Output Refer to Output Drivers section for more details. Negative differential clock output. Included in Bank A. 5 nQA1 Output Refer to Output Drivers section for more details. 6 V Power Output voltage supply for Output Bank A. CCOA Positive differential clock output. Included in Bank A. 7 QA2 Output Refer to Output Drivers section for more details. Negative differential clock output. Included in Bank A. 8 nQA2 Output Refer to Output Drivers section for more details. Positive differential clock output. Included in Bank A. 9 QA3 Output Refer to Output Drivers section for more details. 2020 Renesas Electronics Corporation 2 November 25, 2020 QA3 CLK0 nQA3 nCLK0 nc V CC V IOA0 CC CLK SEL IOB0 nc V CC nQB3 nCLK1 QB3 CLK1