Low Additive Jitter 2:8 Buffer with 8P791208 CMOS / Differential Outputs Datasheet Description Features Accepts input frequencies ranging from 1PPS (1Hz) to 700MHz The 8P791208 is a low additive jitter 2:8 buffer with CMOS/ differential outputs The device takes one or two reference clocks, Two differential inputs support LVPECL, LVDS, LVHSTL, selects between them using a pin selection, and generates up to HCSL, or LVCMOS reference clocks eight outputs that are the same as the reference frequency. Generates 8 differential or 16 LVCMOS outputs The 8P791208 supports two output banks, each with its own Outputs arranged in two banks of four outputs each power supply. All outputs in one bank would generate the same Select pins control which input drives which of two output output frequency, but each output can be individually controlled for banks output type or output enable. Controlled by 3-level input pins that are 3.3V tolerant for all The device can operate over the -40C to 85C temperature core voltages range. Output type may be selected from LVPEC, LVDS or 2xLVCMOS Each bank supports a separate power supply of 3.3V, 2.5V, or 1.8V LVCMOS outputs are limited to 125MHz maximum and support swings of 3.3V, 2.5V, 1.8V, and 1.5V Individual output enables and output type selection supported Output noise floor of 158dBc/Hz at 156.25MHz Core voltage supply of 3.3V, 2.5V, or 1.8V 40C to 85C ambient operating temperature Lead-free (RoHS 6) QFN-32 (5 5mm) packaging Block Diagram 8P791208 transistor count: 9,703 2020 Renesas Electronics Corporation 1 September 21, 20208P791208 Datasheet Contents Description 1 Features 1 Pin Assignments 3 Principles of Operation . 5 Input Selection 5 Output Drivers . 5 LVCMOS Operation 5 Output Enable Control . 6 Supply Voltage Characteristics 7 Applications Information . 15 Recommendations for Unused Input and Output Pins . 15 Inputs 15 Outputs . 15 Wiring the Differential Input to Accept Single-ended Levels . 15 3.3V Differential Clock Input Interface 17 2.5V Differential Clock Input Interface 18 LVDS Driver Termination . 19 Termination for 3.3V LVPECL Outputs . 20 Termination for 2.5V LVPECL Outputs . 21 Power Dissipation and Thermal Considerations . 22 Power Domains . 22 Power Consumption Calculation 22 Thermal Considerations 23 Current Consumption Data and Equations 23 Example Calculations 25 LVPECL Power Considerations (700MHz) . 25 LVDS Power Considerations (700MHz) . 27 LVCMOS Power Considerations (125MHz) 28 Dynamic Power Dissipation at fOUT(max) 28 Package Outline Drawings . 29 Marking Diagram 29 Revision History . 30 2020 Renesas Electronics Corporation 2 September 21, 2020