Programmable Low Additive Jitter 2:8 8P79818 Buffer with Dividers and Universal Outputs Datasheet Description Features The device is intended to take 1 or 2 reference clocks, select Two differential inputs support LVPECL, LVDS, HCSL or LVCMOS between them, using a pin or register selection and generate up to 8 reference clocks outputs that may be the same as the reference frequency or Accepts input frequencies ranging from 1PPS (1Hz) to integer-divider versions of it. 700MHz Select which of the two input clocks is to be used as the reference The 8P79818 supports two output banks, each with its own divider clock for which divider via pin or register selection and power supply. All outputs in one bank would generate the same output frequency, but each output can be individually controlled for Switchover will not generate any runt clock pulses on the output type, output enable or even powered-off. output The device supports a serial port for configuration of the parameters Generates eight differential outputs or eight LVCMOS outputs, 2 while in operation. The serial port can be selected to use the I C or Bank A only SPI protocol. After power-up, all outputs will come up in LVDS mode Differential outputs selectable as LVPECL, LVDS, CML or and may be programmed to other configurations over the serial port. HCSL Outputs may be enabled or disabled under control of the OE input Differential outputs support frequencies from 1PPS to 700MHz pin. LVCMOS outputs support frequencies from 1PPS to 200MHz The device can operate over the -40C to +85C temperature range. LVCMOS outputs in the same pair may be inverted or in-phase relative to one another Outputs arranged in 2 banks of 4 outputs each Each bank supports a separate power supply of 3.3V, 2.5V or 1.8V 1.5V output voltage is also supported for LVCMOS, Bank A only One divider per output bank, supporting divide ratios of 2...511 or divider bypass Output enable control pin Output enable or disable will not cause any runt pulses 2 Register programmable via I C / SPI serial port Individual output enables, output type selection and output power-down control bits supported Input mux selection control bit Core voltage supply of 3.3V, 2.5V or 1.8V -40C to +85C ambient operating temperature Lead-free (RoHS 6) packaging 2021 Renesas Electronics Corporation 1 R31DS0055EU0200 July 29, 20218P79818 Datasheet Block Diagram Figure 1: Block Diagram BankA QA 0 nQA0 DIVA (2to511) QA 1 nQA1 PU CL K S EL QA 2 Divby1 nQA2 PD CL K 0 QA 3 nCLK0 nQA3 PU/ PD BankB QB0 PD CL K 1 nQB0 DIVB nCLK1 (2to511) QB1 PU/ PD nQB1 PU OE QB2 nQB2 Divby1 PU SCLK QB3 nQB3 PU SDAT A/SDI Logic PU SA 0/ nCS PD nI 2C/S PI 8P79818 transistor count: 33,394 2021 Renesas Electronics Corporation 2 R31DS0055EU0200 July 29, 2021