8R9306NLGI Renesas

TM 2.5V LVDS, 1:6 Clock Buffer Terabuffer II IDT8R9306I DATASHEET General Description Features The IDT8R9306I 2.5V differential clock buffer is a user-selectable Guaranteed low skew: 40ps (maximum) differential input to six LVDS outputs. The fanout from a differential Very low duty cycle distortion: <125ps (maximum) input to six LVDS outputs reduces loading on the preceding driver High speed propagation delay: <1.75ns (maximum) and provides an efficient clock distribution network. The IDT8R9306I Up to 1GHz operation can act as a translator from a differential HSTL, eHSTL, LVPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A Selectable inputs single-ended 3.3V, 2.5V LVTTL input can also be used to translate to Hot insertable and over-voltage tolerant inputs LVDS outputs. The redundant input capability allows for an 3.3V/2.5V LVTTL, HSTL eHSTL, LVPECL (2.5V), LVPECL (3.3V), asynchronous change-over from a primary clock source to a CML or LVDS input interface secondary clock source. Selectable reference inputs are controlled Selectable differential inputs to six LVDS outputs by SEL. Power-down mode The IDT8R9306I outputs can be asynchronously enabled/disabled. 2.5V V When disabled, the outputs will drive to the value selected by the GL DD pin. Multiple power and grounds reduce noise. -40C to 85C ambient operating temperature Available in VFQFPN package Applications Clock distribution Pin Assignment 21 20 19 18 17 16 15 nc 22 14 VDD nQ5 23 13 nQ3 24 Q3 Q5 12 GND nQ6 25 nQ2 11 26 10 Q2 Q6 VDD 27 VDD 9 SEL 28 8 GL 123 4 5 6 7 IDT8R9306I 28-LeadVFQFPN 6mm x 6mm x 0.9mm package body EPad 4.8mm x 4.8mm NL Package TopView IDT8R9306NLI REVISION D AUGUST 21, 2013 1 2013 Integrated Device Technology, Inc. nG nPD VDD VDD Q1 Q4 nQ1 nQ4 VDD VDD A1 A2 nA1 nA2IDT8R9306I Data Sheet 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER II Block Diagram GL nG Q1 OUTPUT CONTROL nQ1 nPD Q2 OUTPUT CONTROL nQ2 A1 1 nA1 Q3 OUTPUT CONTROL nQ3 A2 Q4 OUTPUT 0 CONTROL nA2 nQ4 Q5 OUTPUT SEL CONTROL nQ5 Q6 OUTPUT CONTROL nQ6 IDT8R9306NLI REVISION D AUGUST 21, 2013 2 2013 Integrated Device Technology, Inc.