Differential LVPECL-To-LVPECL/ECL 8S89831I Fanout Buffer Datasheet Description Features The 8S89831I is a high speed 1-to-4 Differential- to-LVPECL/ECL Four LVPECL/ECL outputs Fanout Buffer. The 8S89831I is optimized for high speed and very IN, nIN input can accept the following differential input levels: low output skew, making it suitable for use in demanding applications LVPECL, LVDS, CML, SSTL such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fiber 50 internal input termination to V T Channel. The internally terminated differential input and VREF AC pin Output frequency: >2.1GHz allow other differential signal families such as LVDS, LVHSTL and Output skew: 30ps (maximum) CML to be easily interfaced to the input with minimal use of external components. Part-to-part skew: 185ps (maximum) The device also has an output enable pin which may be useful for Additive phase jitter, RMS: 0.31ps (typical) system test and debug purposes. The 8S89831I is packaged in a Propagation Delay: 570ps (maximum) small 3mm x 3mm 16-pin VFQFN package which makes it ideal for LVPECL mode operating voltage supply range: use in space-constrained applications. V = 2.5V5%, 3.3V5%, V = 0V CC EE ECL mode operating voltage supply range: V = 0V, V = -3.3V5%, -2.5V5% CC EE -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Supports 105C board temperature operations Block Diagram Pin Assignment Pullup EN DQ Q0 16 15 14 13 nQ0 Q1 1 12 IN nQ1 2 11 VT Q1 IN 3 Q2 10 VREF AC 50 V nQ1 T nQ2 4 nIN 9 50 nIN 5 6 7 8 Q2 V REF AC nQ2 8S89831I 16-Lead VFQFN Q3 3mm x 3mm x 0.925mm package body nQ3 K Package Top View 2017 Integrated Device Technology, Inc. 1 November 9, 2017 Q3 nQ0 nQ3 Q0 VCC VCC EN VEE8S89831I Datasheet Table 1. Pin Descriptions Number Name Type Description 1, 2 Q1, nQ1 Output Differential output pair. LVPECL/ECL interface levels. 3, 4 Q2, nQ2 Output Differential output pair. LVPECL/ECL interface levels. 5, 6 Q3, nQ3 Output Differential output pair. LVPECL/ECL interface levels. 7, 14 V Power Power supply pins. cc Synchronizing clock enable. When LOW, Qx outputs will go LOW and nQx outputs will go HIGH on the next LOW transition at IN input. Input threshold is V /2. Includes a CC 8 EN Input Pullup 37k pull-up resistor. Default state is HIGH when left floating. The internal latch is clocked on the falling edge of the input signal IN. LVTTL / LVCMOS interface levels. 9 nIN Input Inverting differential LVPECL clock input. RT = 50 termination to V . T 10 V Output Reference voltage for AC-coupled applications. REF AC 11 V Input Termination input. I (max.) < 2mA. T REF AC Non-inverting LVPECL differential clock input. 12 IN Input RT = 50 termination to V . T 13 V Power Negative supply pin. EE 15, 16 Q0, nQ0 Output Differential output pair. LVPECL/ECL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units R Input Pullup Resistor 37 k PULLUP 2017 Integrated Device Technology, Inc. 2 November 9, 2017