Low Phase Noise, 1-to-2, 3.3V, 2.5V 8S LV P1102 LVPECL Output Fanout Buffer Da t as he et Description Features The 8SLVP1102 is a high-performance differential LVPECL fanout Two low skew, low additive jitter LVPECL output pairs buffer. The device is designed for the fanout of high-frequency, very Differential PCLK, nPCLK pair can accept the following differential low additive phase-noise clock and data signals. The 8SLVP1102 is input levels: LVDS, LVPECL, CML characterized to operate from a 3.3V or 2.5V power supply. Maximum input clock frequency: 2GHz Guaranteed output-to-output and part-to-part skew characteristics Output skew: 5ps (typical) make the 8SLVP1102 ideal for those clock distribution applications demanding well-defined performance and repeatability. One Propagation delay: 250ps (maximum) differential input and two low skew outputs are available. The Low additive phase jitter, RMS f = 156.25MHz, V = 1V, REF PP integrated bias voltage reference enables easy interfacing of 12kHz20MHz: 49fs (maximum) single-ended signals to the device input. The device is optimized for Full 3.3V or 2.5V supply voltage low power consumption and low additive phase noise. Maximum device current consumption (I ): 34mA (maximum) EE Available in lead-free (RoHS 6), 16-Lead VFQFPN package -40C to +85C ambient operating temperature Supports case temperature 105C operations Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can also accept single-ended LVCMOS levels. See Applications section Wiring the Differential Input Levels to Accept Single-ended Levels (Figure 1A and Figure 1B) Supports PCI Express Gen15 Block Diagram Pin Assignment V CC 16 15 14 13 VEE 1 12 nQ1 Q0 nQ0 nc 2 11 Q1 PCLK 3 10 nc nQ0 nPCLK Q1 nc 4 Q0 9 nQ1 5 6 7 8 Voltage V REF Reference 8SLVP1102 16-Lead VFQFPN 3.0 3.0 0.9 mm package body NL Package Top View R31DS0033EU0700 May 20, 2021 1 2021 Renesas Electronics Corporation VCC VEE PCLK nc nPCLK nc VREF nc8SLVP1102 DATASHEET Pin Descriptions and Characteristics Table 1. Pin Descriptions Number Name Type Description 1, 16 V Power Negative supply pins. EE 2, 3, 4, nc Unused Do not connect. 13, 14, 15 5 V Power Power supply pin. CC 6 PCLK Input Pulldown Non-inverting differential LVPECL clock/data input. Pullup/ Inverting differential LVPECL clock/data input. V /2 default when left CC 7 nPCLK Input Pulldown/ floating. 8 V Output Bias voltage reference for the PCLK input. REF 9, 10 Q0, nQ0 Output Differential output pair 0. LVPECL interface levels. 11, 12 Q1, nQ1 Output Differential output pair 1. LVPECL interface levels. NOTE: Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 2 pF IN R Input Pulldown Resistor 51 k PULLDOWN R Input Pullup Resistor 51 k PULLUP R31DS0033EU0700 May 20, 2021 2 2021 Renesas Electronics Corporation