1:2 Clock Fanout Buffer and 8T73S1802 Frequency Divider Datasheet Description Features The 8T73S1802 is a fully integrated clock fanout buffer and High-performance fanout buffer clock and fanout buffer frequency divider. The input signal is frequency-divided and then Input clock signal is distributed to one LVPECL and one fanned out to one differential LVPECL and one LVCMOS output. LVCMOS output Each of the outputs can select its individual divider value from the Configurable output dividers for both LVPECL and LVCMOS range of 1, 2, 4 and 8. Three control inputs EN, SEL0 and outputs SEL1 (3-level logic) are available to select the frequency dividers and the output enable/disable state. The single-ended LVCMOS Supports clock frequencies up to 1000MHz (LVPECL) and up to output is phase-delayed by 650ps to minimize coupling of 200MHz (LVCMOS) LVCMOS switching into the differential output during its signal Flexible differential input supports LVPECL, LVDS and CML transition. V generator output supports single-ended input signal BB The 8T73S1802 is optimized to deliver very low phase noise applications clocks. The V output generates a common-mode voltage BB reference for the differential clock input so that connecting the V Optimized for low phase noise BB pin to an unused input (nCLK) enables to use of single-ended input 650ps delay between LVCMOS and LVPECL minimizes coupling signals. The extended temperature range supports wireless between outputs infrastructure, telecommunication and networking end equipment Supply voltage: 3.3V or 2.5V requirements. The 8T73S1802 can be used with a 3.3V or a 2.5V power supply. The device is a member of the high-performance -40C to 85C ambient operating temperature clock family from IDT. 16 VFQFPN package (3 x 3 mm) Block Diagram Pin Assignment 1 11 10 9 12 CLK 2 QA 13 8 SEL0 V CCO QB 4 nCLK nQA 8 7 14 QB GND 8T73S1802 Bias Generator V BB V -1.3V CC 6 15 GND QB SEL1 8XXXXXX Pullup 5 GND 16 EN SEL0 Pullup 1 2 34 SEL1 Control Pullup EN 16-pin, 3mm x 3mm VFQFPN Package 2018 Integrated Device Technology, Inc. 1 January 21, 2018 V V CC CCO QA CLK nQA nCLK QA V BB V CCO QA8T73S1802 Datasheet Pin Description and Pin Characteristic Tables Table 1. Pin Assignment 1 Pin Number Name Type Description 1V Power Power supply voltage for the device core and the inputs. CC Non-inverting differential clock input. Compatible with LVPECL, 2 CLK Input LVDS and CML signals. Inverting differential clock input. Compatible with LVPECL, LVDS 3 nCLK Input and CML signals. Bias voltage generator output. Use to bias the nCLK input in 4V Output BB single-ended input applications. V = V - 1.3V. BB CC Ground supply voltage (GND) and ground return path. Connect to 5 GND Power board GND (0V). Ground supply voltage (GND) and ground return path. Connect to 6 GND Power board GND (0V). LVCMOS clock output QB. LVCMOS/LVTTL interface levels. 7 QB Output If this pin is disabled by connecting its power supply pin V to CCO QB GND, QB must be left open or connected to GND. Positive supply voltage for the QB output. The QB output (if not 8V Power CCO QB connected) can be disabled by connecting this pin to GND. Positive supply voltage for the QA, nQA output. The QA, nQA output 9V Power CCO QA (if not connected) can be disabled by connecting this pin to GND. Differential clock output QA. LVPECL interface levels. 10 QA Output If this pin is disabled by connecting its power supply pins V to CCO QA GND, QA and nQA must be left open or connected to GND. Differential clock output QA. LVPECL interface levels. 11 nQA Output If this pin is disabled by connecting its power supply pins V to CCO QA GND, QA and nQA must be left open or connected to GND. Positive supply voltage for the QA, nQA output. The QA, nQA output 12 V Power CCO QA (if not connected) can be disabled by connecting this pin to GND. Configuration pins. 3-Level interface. See Table 3 for function and 13 SEL0 Input 60k Pullup Table 4D for interface levels. Ground supply voltage (GND) and ground return path. Connect to 14 GND Power board GND (0V). Configuration pins. 3-Level interface. See Table 3 for function and 15 SEL1 Input 60k Pullup Table 4D for interface levels. Configuration pin. 3-Level interface. See Table 3 for function and 16 EN Input 60k Pullup Table 4D for interface levels. NOTE 1. Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 2 pF IN Power C 5.4 pF PD Dissipation Capacitance R Input Pullup Resistor 42 60 78 k PULLUP V = 2.375V 38 LVCMOS CCO QB R OUT Output Resistance V = 3.465V 28 CCO QB 2018 Integrated Device Technology, Inc. 2 January 21, 2018