1-to-8 Differential to Universal Output IDT8T79S818I-08 Clock Divider/Fanout Buffer DATASHEET General Description Features The IDT8T79S818I-08 is a high performance, 1-to-8, differential input Four banks of two low skew outputs to universal output clock divider and fanout buffer. The device is Selectable bank output divider values: 1 through 6 and 8 designed for frequency-division and signal fanout of high-frequency One differential PCLK, nPCLK input clock signals in applications requiring four different output PCLK, nPCLK input pair can accept the following differential input frequencies generated simultaneously. Each bank of two outputs has levels: LVPECL, LVDS levels a selectable divider value of 1 through 6 and 8. The Maximum input frequency: 1.5GHz IDT8T79S818I-08 is optimized for 3.3V and 2.5V supply voltages and a temperature range of -40C to 85C. The device is packaged in a LVCMOS control inputs space-saving 32 lead VFQFN package. QXx 1 edge aligned to QXx n edge Individual output divider control via serial interface Individual output enable/disable control via serial interface Individual output type control, LVDS or LVPECL, via serial interface 2.375V to 3.465V supply voltage operation -40C to 85C ambient operating temperature Lead-free (RoHS 6) packaging Pin Assignment Block Diagram VCC QA0 nQA0 Pulldown PCLK 7 Dividers Pullup/Pulldown nPCLK QA1 V 25 16 V RST nQA1 CC CC VEE VEE V 26 15 V EE EE QB0 IDT8T79S818I-08 nQA1 27 14 QD0 nQB0 32 lead VFQFN QA1 28 13 nQD0 QB1 5mm x 5mm x 0.925mm nQB1 nQA0 29 12 QD1 Pad size 3.15mm x 3.15mm NL package QA0 30 11 nQD1 QC0 Top View nQC0 Pulldown VCC 31 10 VCC PWR SEL QC1 SDATA 32 9 PWR SEL nQC1 VEE QD0 nQD0 VCC QD1 nQD1 Pullup nRST Pulldown OE Divider Select, 12 O utput Type and Pulldown LE 10 O utput Enable Pulldown SCLK logic Pulldown MISO SDATA VEE VEE VEE VEE IDT8T79S818A-08NLGI REVISION A JULY 11, 2013 1 2013 Integrated Device Technology, Inc. SCLK QBO nQB0 MISO QB1 nRST nQB1 PCLK QC0 nPCLK OE nQC0 V QC1 CC LE nQC1 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17IDT8T79S818I-08 Data Sheet 1-TO-8 DIFFERENTIAL TO UNIVERSAL OUTPUT, CLOCK DIVIDER/FANOUT BUFFER Pin Description and Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1 SCLK Input Pulldown Serial Control Port Mode Data Input. LVCMOS/LVTTL interface levels. 2 Output Serial Control Port Mode Data Output. LVCMOS/LVTTL interface levels. MISO Frequency Divider Reset. When the nRST is released (rising edge), the divided clock outputs are activated and will transition to a high state simultaneously. 3 nRST Input Pullup See also Timing Diagram. LVCMOS/LVTTL interface levels (Figure 1. Timing Diagram). 4 PCLK Input Pulldown Non-inverting differential clock input. Pullup / 5 Input Inverting differential clock input. V / 2 by default when left floating. nPCLK CC Pulldown Default output disable. LVCMOS/LVTTL interface levels. See Table 3B. OE 6 Input Pulldown OE Truth Table. 7, 10, 16, Power Power supply voltage pin. V CC 25, 31 Serial Control Port Mode Load Enable. Latches data when the pin gets a high 8 LE Input Pulldown level. Outputs are disabled when LE is low. LVCMOS/LVTTL interface levels. 9 Pulldown Power supply selection. See Table 3A. PWR SEL Truth Table. PWR SEL 11, 12 nQD1, QD1 Output Differential output pair Bank D, output 1. LVPECL or LVDS interface levels. 13, 14 Output Differential output pair Bank D, output 0. LVPECL or LVDS interface levels. nQD0, QD0 15, 26 Power Negative power supply pins. V EE 17, 18 nQC1, QC1 Output Differential output pair Bank C, output 1. LVPECL or LVDS interface levels. 19, 20 Output Differential output pair Bank C, output 0. LVPECL or LVDS interface levels. nQC0, QC0 21, 22 Output Differential output pair Bank B, output 1. LVPECL or LVDS interface levels. nQB1, QB1 23, 24 nQB0, QB0 Output Differential output pair Bank B, output 0. LVPECL or LVDS interface levels. 27, 28 Output Differential output pair Bank A, output 1. LVPECL or LVDS interface levels. nQA1, QA1 29, 30 Output Differential output pair Bank A, output 0. LVPECL or LVDS interface levels. nQA0, QA0 32 SDATA Input Pulldown Serial Control Port Mode Data Input. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2. Pin Characteristics for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 2pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN V = 3.3V 125 CC R Output Impedance MISO OUT V = 2.5V 145 CC IDT8T79S818A-08NLGI REVISION B JULY 11, 2013 2 2013 Integrated Device Technology, Inc.