1-to-8 Differential to Universal Output IDT8T79S838-08I Fanout Buffer DATA SHEET General Description Features The IDT8T79S838-08I is a high performance, 1-to-8, differential input Four banks of two output pairs to universal output fanout buffer. The device is designed for signal Individual output type control, LVDS or LVPECL, via fanout of high-frequency clock signals in applications requiring output serial interface frequencies generated simultaneously. The IDT8T79S838-08I is Individual outputs remain enabled while serial loading new optimized for 3.3V and 2.5V supply voltages and a temperature range device configurations of -40C to 85C. The device is packaged in a space-saving 32 lead One differential PCLK, nPCLK input VFQFN package. PCLK, nPCLK input pair can accept the following differential input levels: LVPECL, LVDS levels Maximum input frequency: 1.5GHz LVCMOS control inputs Individual output enable/disable control via serial interface 2.375V to 3.465V supply voltage operation -40C to 85C ambient operating temperature Lead-free (RoHS 6) packaging Block Diagram Pin Assignment QA0 nQA0 VCC V 25 16 V CC CC QA1 VEE 26 15 VEE nQA1 Pulldown PCLK IDT8T79S838-08I Pullup / Pulldown nQA1 27 14 QD0 nPCLK QB0 32 lead VFQFN QA1 28 13 nQD0 nQB0 5mm x 5mm x 0.925mm VEE VEE nQA0 29 12 QD1 Pad size 3.15mm x 3.15mm QB1 NL package QA0 30 11 nQD1 nQB1 Top View V 31 10 V CC CC QC0 SDATA 32 9 PWR SEL nQC0 Pulldown PWR SEL QC1 nQC1 VEE QD0 nQD0 QD1 nQD1 Pulldown OE Output Type and Pulldown LE Output Enable Pulldown logic SCLK Pulldown SDATA MISO VEE VEE VEE VEE IDT8T79S838-08NLGI REVISION A JANUARY 29, 2014 1 2014 Integrated Device Technology, Inc. SCLK QBO MI nQB0 SO nc QB1 nQB1 PCLK nPCLK QC0 nQC0 OE V QC1 CC nQC1 LE 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17IDT8T79S838-08I Data Sheet 1-to-8 Differential to Universal Output Fanout Buffer Pin Description and Pin Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1 SCLK Input Pulldown Serial Control Port Mode Data Input. LVCMOS/LVTTL interface levels. 2 MISO Output Serial Control Port Mode Data Output. LVCMOS/LVTTL interface levels. 3 nc Unused No connect. 4 PCLK Input Pulldown Non-inverting differential clock input. Pullup / 5nPCLK Input Inverting differential clock input. V / 2 by default when left floating. CC Pulldown Default output disable. LVCMOS/LVTTL interface levels. 6 OE Input Pulldown See Table 3B. OE Truth Table. 7, 10, 16, 25, 31 V Power Power supply voltage pin. CC Serial Control Port Mode Enable. Latches data when the pin gets a high level. 8 LE Input Pulldown Outputs remain enabled when LE is low. LVCMOS/LVTTL interface levels. 9 PWR SEL Input Pulldown Power supply selection. See Table 3A. PWR SEL Truth Table. 11, 12 nQD1, QD1 Output Differential Bank D output pair. 13, 14 nQD0, QD0 Output Differential Bank D output pair. 15, 26 V Power Negative power supply pins. EE 17, 18 nQC1, QC1 Output Differential Bank C output pair. LVPECL or LVDS interface levels. 19, 20 nQC0, QC0 Output Differential Bank C output pair. LVPECL or LVDS interface levels. 21, 22 nQB1, QB1 Output Differential Bank B output pair. LVPECL or LVDS interface levels. 23, 24 nQB0, QB0 Output Differential Bank B output pair. LVPECL or LVDS interface levels. 27, 28 nQA1, QA1 Output Differential Bank A output pair. LVPECL or LVDS interface levels. 29, 30 nQA0, QA0 Output Differential Bank A output pair. LVPECL or LVDS interface levels. 32 SDATA Input Pulldown Serial Control Port Mode Data Input. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2. Pin Characteristics for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 2 pF IN Input Pulldown Resistor 51 k R PULLDOWN R Input Pullup Resistor 51 k PULLUP V = 3.3V 125 CC R Output Impedance MISO OUT V = 2.5V 125 CC IDT8T79S838-08NLGI REVISION A JANUARY 29, 2014 2 2014 Integrated Device Technology, Inc.