Clock Fanout Buffer/Frequency Divider 8V74S4622 DATA SHEET General Description Features The 8V74S4622 is a versatile Clock Fanout Buffer/Frequency Clock signal selection, frequency-division and distribution Divider. The device supports the selection, division and distribution Two outputs individually select: of high-frequency clock signals with very low additive phase noise. The 8V74S4622 uses SiGe technology for an optimum of high clock The input signal 2, 4, 5 and 8 or frequency and low phase noise performance, combined with high The input signal without frequency division (input signal is power supply noise rejection and internal isolation. passed through) Two selectable inputs are supported for differential and single ended clocks. Each of the two outputs can select a copy or a frequency- Two inputs to support single-ended and differential operation divided input signal. The available frequency divisions are divide-by-2, 4, 5 and 8. Both outputs support LVDS interfaces. For Differential input supports LVDS and LVPECL signals each of the two outputs, a synchronous output enabled control is Single-ended input supports LVCMOS signals implemented for stopping the output clock synchronously to the input clock signal. All device configurations are through a logic pin Two differential LVDS outputs interface. The device is packaged in a lead-free (RoHS 6) 20-lead VFQFN package. The extended temperature range supports Maximum Input Frequency (differential input clock): 2000MHz wireless infrastructure, telecommunication and networking end Maximum Output Frequency: 2000MHz equipment requirements. The device is a member of the high-performance clock family from IDT. Output skew: 22ps (maximum) Additive phase noise RMS, 125MHz, SELn = 0, 12kHz - 20MHz integration range: 180fs (maximum) LVDS output rise/fall time: 260ps (maximum) 3.3V core and output supply voltages -40C to 85C ambient operating temperature 2 Lead-free (RoHS 6) 4x4 mm 20-lead VFQFN packaging Pin Assignment Block Diagram 20 19 18 17 16 CLK 0 f CLK 1 15 SEL1 nOE0 0 IN 1 Q0 EN 1 nIN nQ0 N 2 14 IN GND 2x 50 0 VT Q1 EN 3 13 VT 8V74S4622 nQ1 1 nQ1 REFSEL N 1:0 2 4 12 nIN Q1 SEL 1:0 2 nOE0 nOE1 5 11 REFSEL V DDO1 6 7 89 10 20-pin,4mmx4mmVFQFNPackage 8V74S4622 REVISION 1 05/11/15 1 2015 Integrated Device Technology, Inc. SEL0 V DD GND CLK N1 Q0 N0 nQ0 nOE1 V DDO08V74S4622 DATA SHEET Pin Descriptions and Characteristics 1 Table 1. Pin Descriptions Number Name Type Description Function select control input. LVCMOS 3.3V interface. 1 SEL1 Input Pulldown SeeTable 3B for function. Differential clock signal non-inverting differential input. Internal termination 2 IN Input 50. Differential clock input termination pin for built-in 50 termination interface. 3 VT See the application information for terminating LVDS and LVPECL input signals. Differential clock signal inverting differential input. 4 nIN Input Internal termination 50. 5 REFSEL Input Pulldown Input select control input. LVCMOS 3.3V interface. SeeTable 3A for function. 6 V Power Positive supply voltage (3.3V). DD 7 CLK Input Pulldown Single-ended LVCMOS 3.3V clock signal input. 8 N1 Input Pullup Frequency divider control input. LVCMOS 3.3V interface. See Table 3C for function. 9 N0 Input Pulldown 3.3V interface. Output Q1 enable control input. LVCMOS 10 nOE1 Input Pullup See Table 3D for function. 11 V Power Positive supply voltage (3.3V) for the Q1 output. DDO1 12 Q1 Output Differential clock output 1. LVDS interface signals. 13 nQ1 Output 14 GND Power Ground supply voltage (0V). Connect to board GND. Output Q0 enable control input. LVCMOS 3.3V interface. 15 nOE0 Input Pullup See Table 3D for function. 16 V Power Positive supply voltage (3.3V) for the Q0 output. DDO0 17 nQ0 Output Differential clock output 0. LVDS interface signals. 18 Q0 Output 19 GND Power Ground supply voltage (0V). Connect to board GND. Function select control input. LVCMOS 3.3V interface. 20 SEL0 Input Pulldown See Table 3B for function. GND Power Exposed package ground supply voltage (GND). Connect to board GND. NOTE: 1. Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 2 pF IN R Input Pullup Resistor 50 k PULLUP R Input Pulldown Resistor 50 k PULLDOWN CLOCK FANOUT BUFFER/FREQUENCY DIVIDER 2 REVISION 1 05/11/15