ICS91309 High Performance Communication Buffer General Description Features The ICS91309 is a high performance, low skew, low jitter Zero input - output delay zero delay buffer. It uses a phase lock loop (PLL) Frequency range 10 - 133 MHz (3.3V) technology to align, in both phase and frequency, the REF 5V tolerant input REF input with the CLKOUT signal. It is designed to distribute High loop filter bandwidth ideal for Spread Spectrum high speed clocks in communication systems operating applications. at speeds from 10 to 133 MHz. Less than 125 ps cycle to cycle Jitter Skew controlled outputs The ICS91309 provides synchronization between the Available in 16 pin, 150 mil SSOP, SOIC & 4.40mm input and output. The synchronization is established via TSSOP packages CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than +/- 350 pS, the Skew: Group-to-Group: <215 ps part acts as a zero delay buffer. Skew within Group: <100 ps Commercial temperature range: 0C to +70C ICS91309 has two banks of four outputs controlled by two address lines. Depending on the selected address line, bank B or both banks can be put in a tri-state mode. In this mode, the PLL is still running and only the output buffers Pin Configuration are put in a high impedance mode. The test mode shuts off the PLL and connects the input directly to the output REF 1 16 CLKOUT buffers (see table below for functionality). CLKA1 2 15 CLKA4 ICS91309 comes in a 16-pin 150 mil SOIC, SSOP or CLKA2 3 14 CLKA3 4.40mm TSSOP package. In the absence of REF input, the device will enter a powerdown mode. In this mode, the VDD 4 13 VDD PLL is turned off and the output buffers are pulled low. GND 5 12 GND Power down mode provides the lowest power consumption for a standby condition. CLKB1 6 11 CLKB4 CLKB2 7 10 CLKB3 FS2 8 9 FS1 Block Diagram 16 pin SSOP, SOIC & TSSOP Functionality Ouput PLL FS2 FS1 CLKA(1:4) CLKB(1:4) CLKOUT Source Shutdown 0 0 Tristate Tristate Driven PLL N 0 1 Driven Tristate Driven PLL N PLL PLL PLL Bypass 10 REF Y Bypass Bypass Mode Mode Mode 1 1 Driven Driven Driven PLL N 0093H12/09/08 ICS91309ICS91309 Pin Descriptions PIN PIN NAME PIN TYPE DESCRIPTION 1 1 IN Input reference frequency, 5V tolerant input REF 2 2 OUT Buffered clock output, Bank A CLKA1 2 3 OUT Buffered clock output, Bank A CLKA2 4, 13 VDD PWR Power Supply 5, 12 GND PWR Ground 2 6 OUT Buffered clock output, Bank B CLKB1 2 7 OUT Buffered clock output, Bank B CLKB2 3 8 IN Function select input, bit 2 FS2 3 9 IN Function select input, bit 1 FS1 2 10 OUT Buffered clock output, Bank B CLKB3 2 11 OUT Buffered clock output, Bank B CLKB4 2 14 CLKA3 OUT Buffered clock output, Bank A 2 15 OUT Buffered clock output, Bank A CLKA4 2 16 OUT Buffered clock output, internal feedback CLKOUT Notes: 1. Weak pull-down 2. Weak pull-down on all outputs 3. Weak pull-ups on these inputs 0093H12/09/08 2