DATASHEET ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 Description Features/Benefits CLKREQ pin for outputs 1 and 4/output enable for Express The ICS9DB102 zero-delay buffer supports PCI Express Card applications clocking requirements. The ICS9DB102 is driven by a differential SRC output pair from an ICS CK410/CK505-compliant main PLL or bypass mode/PLL can dejitter incoming clock clock. It attenuates jitter on the input clock and has a selectable Selectable PLL bandwidth/minimizes jitter peaking in PLL Band Width to maximize performance in systems with or downstream PLLs without Spread-Spectrum clocking. Spread Spectrum Compatible/tracks spreading input clock for low EMI SMBus Interface/unused outputs can be disabled Industrial temperature range available Output Features 2 - 0.7V current mode differential output pairs (HCSL) Key Specifications Cycle-to-cycle jitter < 35ps Output-to-output skew < 25ps Functional Block Diagram CLKREQ0 CLKREQ1 PCIEX0 CLK INT SPREAD COMPATIBLE PLL PCIEX1 PLL BW CONTROL SMBDAT LOGIC SMBCLK IREF IDT Two Output Differential Buffer for PCIe Gen1 & Gen2 852 REV Q 08/27/13 1 CLK INCICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 Pin Configuration Power Groups Pin Number PLL BW 1 20 VDDA Description VDD GND CLK INT 2 19 GNDA 5,9,12,16 6,15 PCI Express Outputs CLK INC 3 18 IREF SMBUS 96 vCLKREQ0 4 17 vCLKREQ1 20 19 IREF VDD 5 16 VDD 20 19 Analog VDD & GND for PLL core GND 6 15 GND PCIEXT0 7 14 PCIEXT1 PCIEXC0 8 13 PCIEXC1 VDD 9 12 VDD 10 11 SMBCLK SMBDAT Note: Pins preceeded by v have internal 120K ohm pull down resistors 20-pin SSOP & TSSOP Pin Description PIN PIN NAME PIN TYPE DESCRIPTION 3.3V input for selecting PLL Band Width 1PLL BW IN 0 = low, 1= high 2 CLK INT IN True Input for differential reference clock. 3 CLK INC IN Complementary Input for differential reference clock. Output enable for PCI Express output pair 0. 4 vCLKREQ0 IN 0 = enabled, 1 =disabled 5 VDD PWR Power supply, nominal 3.3V 6 GND PWR Ground pin. 7 PCIEXT0 OUT True clock of differential PCI Express pair. 8 PCIEXC0 OUT Complementary clock of differential PCI Express pair. 9 VDD PWR Power supply, nominal 3.3V 10 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant 11 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant 12 VDD PWR Power supply, nominal 3.3V 13 PCIEXC1 OUT Complementary clock of differential PCI Express pair. 14 PCIEXT1 OUT True clock of differential PCI Express pair. 15 GND PWR Ground pin. 16 VDD PWR Power supply, nominal 3.3V Output enable for PCI Express output pair 1. 17 vCLKREQ1 IN 0 = enabled, 1 =disabled This pin establishes the reference for the differential current-mode output pairs. It requires a fixed precision resistor to ground. 475ohm is 18 IREF OUT the standard value for 100ohm differential impedance. Other impedances require different values. See data sheet. 19 GNDA PWR Ground pin for the PLL core. 20 VDDA PWR 3.3V power for the PLL core. Note: Pins preceeded by v have internal 120K ohm pull down resistors IDT Two Output Differential Buffer for PCIe Gen1 & Gen2 852 REV Q 08/27/13 2 ICS9DB102