9DB106BGILFT Renesas

DATASHEET 9DB106 Six Output Differential Buffer for PCIe Gen 2 Description Features/Benefits The 9DB106 zero-delay buffer supports PCIe Gen1 and Gen2 CLKREQ pin for outputs 1 and 4/ supports Express Card clocking requirements. The 9DB106 is driven by a differential SRC applications output pair from an IDT CK410/CK505-compliant main clock PLL or bypass mode/PLL can dejitter incoming clock generator. It attenuates jitter on the input clock and has a selectable Selectable PLL bandwidth/minimizes jitter peaking in PLL bandwidth to maximize performance in systems with or without downstream PLL s Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request Spread Spectrum Compatible/tracks spreading input clock (CLKREQ ) pins make the 9DB106 suitable for Express Card for low EMI applications. SMBus Interface/unused outputs can be disabled Recommended Applications Key Specifications 6 Output Differential Buffer for PCIe Gen 2 Cycle-to-cycle jitter < 50ps Output-to-output skew < 50 ps Output Features 6 - 0.7V current mode differential output pairs (HCSL) Functional Block Diagram CLKREQ1 CLKREQ4 PCIEX1 CLK INT SPREAD COMPATIBLE PLL PCIEX4 PCIEX(0,2,3,5) PLL BW CONTROL SMBDAT LOGIC SMBCLK IREF IDT Six Output Differential Buffer for PCIe Gen 2 9DB106 REV L 05/24/12 1 CLK INC9DB106 Six Output Differential Buffer for PCIe Gen 2 Pin Configuration PLL BW 1 28 VDDA CLK INT 2 27 GNDA CLK INC 3 26 IREF vCLKREQ1 4 25 vCLKREQ4 PCIEXT0 5 24 PCIEXT5 PCIEXC0 6 23 PCIEXC5 VDD 7 22 VDD GND 8 21 GND PCIEXT1 9 20 PCIEXT4 PCIEXC1 10 19 PCIEXC4 PCIEXT2 11 18 PCIEXT3 PCIEXC2 12 17 PCIEXC3 VDD 13 16 VDD 14 15 SMBCLK SMBDAT Note:Pins preceeded by v have internal 120K ohm pull down resistors 28-pin SSOP & TSSOP Power Groups Pin Number Description VDD GND 7, 13, 16, 22 8,21 PCI Express Outputs TBD TBD SMBUS N/A 27 IREF 28 27 Analog VDD & GND for PLL core IDT Six Output Differential Buffer for PCIe Gen 2 9DB106 REV L 05/24/12 2 9DB106