Integrated ICS9DB108 Circuit (Not recommended for new designs) Systems, Inc. Eight Output Differential Buffer for PCI-Express Recommended Application: Pin Configuration DB800 Intel Yellow Cover part with PCI-Express support. SRC DIV 1 48 VDDA VDD 2 47 GNDA Output Features: GND 3 46 IREF 8 - 0.7V current-mode differential output pairs SRC IN 4 45 LOCK Supports zero delay buffer mode and fanout mode SRC IN 5 44 OE 7 Bandwidth programming available OE 0 6 43 OE 4 OE 3742 DIF 7 Key Specifications: 841 DIF 0 DIF 7 Outputs cycle-cycle jitter < 50ps DIF 0 940 GND Outputs skew: 50ps 10 39 VDD GND +/- 300ppm frequency accuracy on output clocks VDD 11 38 DIF 6 DIF 1 12 37 DIF 6 Features/Benefits: 13 36 OE 6 DIF 1 Supports tight ppm accuracy clocks for Serial-ATA OE 1 14 35 OE 5 Spread spectrum modulation tolerant, 0 to -0.5% down OE 2 15 34 DIF 5 spread and +/- 0.25% center spread 16 33 DIF 2 DIF 5 Supports undriven differential output pair in PD and DIF 2 17 32 GND SRC STOP for power management. GND 18 31 VDD 19 30 VDD DIF 4 DIF 3 20 29 DIF 4 DIF 3 21 28 HIGH BW 22 27 SRC STOP BYPASS /PLL SCLK 23 26 PD 24 25 GND SDATA 48-pin SSOP & TSSOP 0723G12/02/08 Not recommended for new designs ICS9DB108Integrated ICS9DB108 Circuit (Not recommended for new designs) Systems, Inc. Pin Description PIN PIN NAME PIN TYPE DESCRIPTION Active low Input for determining SRC output frequency SRC or 1SRC DIV IN SRC/2. 0 = SRC/2, 1= SRC 2 VDD PWR Power supply, nominal 3.3V 3 GND PWR Ground pin. 4 SRC IN IN 0.7 V Differential SRC TRUE input 5 SRC IN IN 0.7 V Differential SRC COMPLEMENTARY input Active high input for enabling outputs. 6OE 0 IN 0 = tri-state outputs, 1= enable outputs Active high input for enabling outputs. 7OE 3 IN 0 = tri-state outputs, 1= enable outputs 8 DIF 0 OUT 0.7V differential true clock outputs 9 DIF 0 OUT 0.7V differential complement clock outputs 10 GND PWR Ground pin. 11 VDD PWR Power supply, nominal 3.3V 12 DIF 1 OUT 0.7V differential true clock outputs 13 DIF 1 OUT 0.7V differential complement clock outputs Active high input for enabling outputs. 14 OE 1 IN 0 = tri-state outputs, 1= enable outputs Active high input for enabling outputs. 15 OE 2 IN 0 = tri-state outputs, 1= enable outputs 16 DIF 2 OUT 0.7V differential true clock outputs 17 DIF 2 OUT 0.7V differential complement clock outputs 18 GND PWR Ground pin. 19 VDD PWR Power supply, nominal 3.3V 20 DIF 3 OUT 0.7V differential true clock outputs 21 DIF 3 OUT 0.7V differential complement clock outputs Input to select Bypass(fan-out) or PLL (ZDB) mode 22 BYPASS /PLL IN 0 = Bypass mode, 1= PLL mode 23 SCLK IN Clock pin of SMBus circuitry, 5V tolerant. 24 SDATA I/O Data pin for SMBus circuitry, 5V tolerant. 0723G12/02/08 2