DATASHEET Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, 9DB1200C and FBDIMM Description Features/Benefits DB1200 Rev 2.0 Intel Yellow Cover Device 3 selectable SMBus addresses for easy system expansion Spread spectrum modulation tolerant, 0 to -0.5% down spread and +/- 0.25% center spread General Description The ICS9DB1200 is an Intel DB1200 Differential Buffer Supports undriven differential outputs in Power Down Mode Specification device. This buffer provides 12 differential clocks for power management. at frequencies ranging from 100MHz to 400 MHz. The ICS9DB1200 is driven by a differential output from a CK410B+ or CK509B main clock generator. Key Specifications Output cycle-cycle jitter < 50ps. Output Features Output to output skew: 50ps 12 - 0.7V current-mode differential output pairs. Phase jitter: PCIe Gen2 < 3.1ps rms Supports zero delay buffer mode and fanout mode. Phase jitter: QPI < 0.5ps rms Bandwidth programming available. 64-pin TSSOP Package 100-400 MHz operation in PLL mode Available in RoHS compliant packaging 33-400 MHz operation in Bypass mode Functional Block Diagram 12 OE (11:0) SPREAD SRC IN COMPATIBLE PLL SRC IN M 12 U DIF(11:0)) X FS(2:0) HIGH BW BYPASS /PLL CONTROL VTTPWRGD /PD LOGIC ADR SEL SMBDAT SMBCLK IREF IDT Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM 1414G08/15/12 19DB1200C Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM Pin Configuration VDD 1 64 VDDA DIF IN 2 63 AGND DIF IN 3 62 IREF GND 4 61 FS0 OE0 5 60 OE11 DIF 0 6 59 DIF 11 DIF 0 7 58 DIF 11 VDD 8 57 VDD GND 9 56 GND OE1 10 55 OE10 DIF 111 54DIF 10 DIF 1 12 53 DIF 10 OE2 13 52 OE9 DIF 214 51DIF 9 DIF 2 15 50 DIF 9 GND 16 49 GND VDD 17 48 VDD OE3 18 47 OE8 DIF 319 46DIF 8 DIF 3 20 45 DIF 8 OE4 21 44 OE7 DIF 422 43DIF 7 DIF 4 23 42 DIF 7 VDD 24 41 VDD GND 25 40 GND OE5 26 39 OE6 DIF 527 38DIF 6 DIF 5 28 37 DIF 6 **ADR SEL29 36VTTPWRGD /PD HIGH BW 30 35 BYPASS /PLL FS231 34FS1 SMBCLK 32 33 SMBDAT 64-TSSOP ** Indicates 120K ohm Pulldown SMBus Address Selection (Pin 29) ADR SEL Voltage SMBus Adr (Wr/Rd) Frequency Select Table Low <0.8V DC/DD FS 2 FS 1 FS 0 Input DIF x L L L MHz MHz Mid 1.2<Vin<1.8V D6/D7 B0b2 B0b1 B0b0 High Vin > 2.0V D4/D5 0 0 0 266.66 266.66 0 0 1 133.33 133.33 Power Groups 0 1 0 200.00 200.00 Pin Number 0 1 1 166.66 166.66 Description VDD GND 1 0 0 333.33 333.33 1 4 DIF IN/DIF IN 1 0 1 100.00 100.00 1 1 0 400.00 400.00 8, 17, 24, 41, 9, 16, 25, 40, DIF(11:0) 1 1 1 Hi-Z Hi-Z 48, 57 49, 56 1. FS (2:0) are 3.3V tolerant low-threshold inputs. N/A 63 IREF L Please see VIL FS and VIH FS specifications in Analog VDD & GND 64 63 the Input/Supply/Common Output Parameters Table for correct values. for PLL core Note: Please treat pin 1 as an analog VDD. IDT Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM 1414G08/15/12 2 9DB1200C