9DB1233AGLF Renesas

12-Output Differential Buffer for 9DB1233 PCIe Gen3 Datasheet Description Features 3 selectable SMBus addresses multiple devices can share the The 9DB1233 zero-delay buffer supports PCIe Gen3 same SMBus segment requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB1233 is driven by a differential SRC output 12 OE pins hardware control of each output pair from an IDT 932S421 or 932SQ420 or equivalent main clock PLL or bypass mode PLL can dejitter incoming clock generator. It attenuates jitter on the input clock and has a Selectable PLL bandwidth minimizes jitter peaking in selectable PLL bandwidth to maximize performance in systems downstream PLLs with or without spread-spectrum clocking. Spread spectrum compatible tracks spreading input clock for low EMI Typical Applications SMBus interface unused outputs can be disabled 12-output PCIe Gen3 zero-delay/fanout buffer Undriven differential outputs in Power-down improved power management Output Features Key Specifications Twelve 0.7V current mode differential HSCL output pairs Cycle-to-cycle jitter < 50ps Output-to-output skew < 50ps PCIe Gen3 phase jitter < 1.0ps RMS Pin compatible with DB1200 Yellow Cover device Block Diagram 12 OE (11:0) SPREAD DIF IN COMPATIBLE PLL DIF IN M 12 DIF(11:0)) U X HIGH BW BYPASS /PLL CONTROL VTTPWRGD /PD LOGIC ADR SEL SMBDAT SMBCLK IREF 2019 Renesas Electronics Corporation 1 December 17, 20199DB1233 Datasheet Contents Description 1 Typical Applications . 1 Output Features 1 Features 1 Key Specifications 1 Block Diagram . 1 Pin Assignments 3 Pin Descriptions 4 Absolute Maximum Ratings . 6 Electrical CharacteristicsClock Input Parameters 6 Electrical CharacteristicsCurrent Consumption . 6 Electrical CharacteristicsInput/Supply/Common Parameters . 7 Electrical CharacteristicsDIF 0.7V Current Mode Differential Outputs 8 Electrical CharacteristicsOutput Duty Cycle, Jitter, Skew and PLL Characteristics 8 Electrical CharacteristicsPCIe Phase Jitter Parameters . 9 Clock Periods Differential Outputs with Spread Spectrum Enabled . 9 Clock Periods Differential Outputs with Spread Spectrum Disabled 9 Terminations 10 General SMBus Serial Interface Information . 12 Package Outline Drawings . 15 Marking Diagram 15 Ordering Information . 15 Revision History . 15 2019 Renesas Electronics Corporation 2 December 17, 2019