SMB A1 SMB A0 DIF 8 DIF 8 OE8 DIF 7 DIF 7 OE7 GND VDD DIF 6 DIF 6 OE6 DIF 5 DIF 5 OE5 SMBDAT SMBCLK Datasheet 19 Output Differential Buffer for PCIe Gen2 and QPI 9DB1904B Description Features/Benefits The 9DB1904 is electrically compatible to the Intel DB1900GS Power up default is all outputs in 1:1 mode/No SMBus Differential Buffer Specification. This buffer provides 19 output clocks programming for PCI-Express Gen2 or Intel QPI 6.4GT/s applications. A differential Spread spectrum compatible/EMI reductions clock from a CK410B+ main clock generator, such as the ICS932S421 drives the 9DB1904. The 9DB1904 can provide Supports output frequencies up to 400 MHz in bypass outputs up to 400MHz in Bypass Mode. mode/flexible fanout buffer 8 Selectable SMBus addresses/no SMBus Recommended Application segmentation required 19 Output Differential Buffer for PCIe Gen2 and QPI SMBus address determines PLL or Bypass mode/pin savings Dedicated VDDA and CKPWRGD PD pins/easy board Key Specifications design DIF output cycle-to-cycle jitter < 50ps DIF output-to-output skew < 150ps across all outputs Functionality at Power Up (PLL Mode) Power Down Functionality INPUTS OUTPUTS CLK IN DIF (18:0) 100M 133M PLL State CKPWRGD CLK IN/ MHz MHz PD CLK IN DIF/DIF 1 100MHz CLK IN 1 Running Running ON 0 133MHz CLK IN 0X Hi-Z OFF Pin Configuration 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 IREF 1 54 OE14 GNDA 2 53 DIF 13 VDDA 3 52DIF 13 HIGH BW 4 51 OE13 100M 133M LV 5 50 DIF 12 DIF 0 6 49 DIF 12 DIF 0 7 48 OE12 DIF 1 8 47 VDD DIF 1 9 46 GND 9DB1904BKLF GND 10 45 DIF 11 VDD 11 44 DIF 11 DIF 2 12 43 OE11 DIF 2 13 42 DIF 10 DIF 3 14 41 DIF 10 DIF 3 15 40 OE10 DIF 4 16 39 DIF 9 DIF 4 17 38 DIF 9 OE 01234 18 37 OE9 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 IDT 19 Output Differential Buffer for PCIe Gen2 and QPI 1607C 04/19/11 1 SMB A2 PLLBYP CLK IN CLK IN OE17 18 DIF 18 DIF 18 DIF 17 DIF 17 GND VDD DIF 16 DIF 16 OE15 16 DIF 15 DIF 15 CKPWRGD PD DIF 14 DIF 149DB1904B 19 Output Differential Buffer for PCIe Gen2 and QPI Pin Description PIN PIN NAME PIN TYPE DESCRIPTION This pin establishes the reference for the differential current-mode output pairs. It requires a fixed precision resistor to ground. 475ohm is the standard 1 IREF OUT value for 100ohm differential impedance. Other impedances require different values. See data sheet. 2 GNDA PWR Ground pin for the PLL core. 3 VDDA PWR 3.3V power for the PLL core. 3.3V input for selecting PLL Band Width 4HIGH BW IN 0 = High, 1= Low Low Threshold Input to select operating frequency. 5 100M 133M LV IN See Functionality Table for Definition 6 DIF 0 OUT 0.7V differential true clock output 7 DIF 0 OUT 0.7V differential Complementary clock output 8 DIF 1 OUT 0.7V differential true clock output 9 DIF 1 OUT 0.7V differential Complementary clock output 10 GND PWR Ground pin. 11 VDD PWR Power supply, nominal 3.3V 12 DIF 2 OUT 0.7V differential true clock output 13 DIF 2 OUT 0.7V differential Complementary clock output 14 DIF 3 OUT 0.7V differential true clock output 15 DIF 3 OUT 0.7V differential Complementary clock output 16 DIF 4 OUT 0.7V differential true clock output 17 DIF 4 OUT 0.7V differential Complementary clock output Active low input for enabling DIF pairs 0, 1, 2, 3 and 4. 18 OE 01234 IN 1 =disable outputs, 0 = enable outputs 19 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant 20 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant Active low input for enabling DIF pair 5. 21 OE5 IN 1 =disable outputs, 0 = enable outputs 22 DIF 5 OUT 0.7V differential true clock output 23 DIF 5 OUT 0.7V differential Complementary clock output Active low input for enabling DIF pair 6. 24 OE6 IN 1 =disable outputs, 0 = enable outputs 25 DIF 6 OUT 0.7V differential true clock output 26 DIF 6 OUT 0.7V differential Complementary clock output 27 VDD PWR Power supply, nominal 3.3V 28 GND PWR Ground pin. Active low input for enabling DIF pair 7. 29 OE7 IN 1 =disable outputs, 0 = enable outputs 30 DIF 7 OUT 0.7V differential true clock output 31 DIF 7 OUT 0.7V differential Complementary clock output Active low input for enabling DIF pair 8. 32 OE8 IN 1 =disable outputs, 0 = enable outputs 33 DIF 8 OUT 0.7V differential true clock output 34 DIF 8 OUT 0.7V differential Complementary clock output 35 SMB A0 IN SMBus address bit 0 (LSB) 36 SMB A1 IN SMBus address bit 1 IDT 19 Output Differential Buffer for PCIe Gen2 and QPI 1607C04/19/11 2