DATASHEET Nineteen Output Differential Buffer for PCIe Gen3 9DB1933 Recommended Application Features/Benefits 8 Selectable SMBus Addresses/Mulitple devices can share 19 output PCIe Gen3 zero-delay/fanout buffer the same SMBus Segment 11 dedicated and 3 group OE pins/Hardware control of the General Description outputs The 9DB1933 zero-delay buffer supports PCIe Gen3 PLL or bypass mode/PLL can dejitter incoming clock requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB1933 is driven by a differential SRC output Selectable PLL bandwidth/minimizes jitter peaking in pair from an IDT 932S421, 932SQ420, or equivalent, main downstream PLL s clock generator. It attenuates jitter on the input clock and has a Spread Spectrum Compatible/tracks spreading input clock selectable PLL bandwidth to maximize performance in systems for low EMI with or without Spread-Spectrum clocking. SMBus Interface/unused outputs can be disabled Supports undriven differential outputs in Power Down mode Output Features for power management 19 - 0.7V current mode differential HCSL output pairs Key Specifications Cycle-to-cycle jitter <50ps Output-to-output skew < 150 ps PCIe Gen3 phase jitter < 1.0ps RMS Functional Block Diagram OE(17 18) 13 OE(15 16) OE(14:5) , OE 01234 PLL DIF IN (SS Compatible) 19 DIF IN DIF(18:0) HIGH BW CKPWRGD/PD SMB A0 Logic SMB A1 SMB A2 PLLBYP SMBDAT SMBCLK IREF IDT Nineteen Output Differential Buffer for PCIe Gen3 1676A07/12/10 1SMB A1 SMB A0 DIF 8 DIF 8 OE8 DIF 7 DIF 7 OE7 GND VDD DIF 6 DIF 6 OE6 DIF 5 DIF 5 OE5 SMBDAT SMBCLK 9DB1933 Nineteen Output Differential Buffer for PCIe Gen3 Pin Configuration 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 IREF 1 54 OE14 GNDA 2 53 DIF 13 VDDA 3 52 DIF 13 HIGH BW 4 51 OE13 VDD 5 50 DIF 12 DIF 0 6 49 DIF 12 DIF 0 7 48 OE12 DIF 1 8 47 VDD DIF 1 9 46 GND 9DB1933AKLF GND 10 45 DIF 11 VDD 11 44 DIF 11 DIF 2 12 43 OE11 DIF 2 13 42 DIF 10 DIF 3 14 41 DIF 10 DIF 3 15 40 OE10 DIF 4 16 39 DIF 9 DIF 4 17 38 DIF 9 OE 01234 18 37 OE9 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Power Down Functionality INPUTS OUTPUTS PLL State CKPWRGD/ DIF IN/ PD DIF IN DIF/DIF 1 Running Running ON 0 X Hi-Z OFF Power Groups Pin Number Description VDD GND 3 2 PLL, Analog 5,11,27,47,63 10,28,46,64 DIF clocks IDT Nineteen Output Differential Buffer for PCIe Gen3 1676A07/12/10 2 SMB A2 PLLBYP DIF IN DIF IN OE 17 18 DIF 18 DIF 18 DIF 17 DIF 17 GND VDD DIF 16 DIF 16 OE 15 16 DIF 15 DIF 15 CKPWRGD/PD DIF 14 DIF 14