DATASHEET Six Output Differential Buffer for PCIe Gen3 9DB633 Features/Benefits: Recommended Application: OE pins/Suitable for Express Card applications 6 output PCIe Gen3 zero-delay/fanout buffer PLL or bypass mode/PLL can dejitter incoming clock Selectable PLL bandwidth/minimizes jitter peaking in General Description: downstream PLL s The 9DB633 zero-delay buffer supports PCIe Gen3 Spread Spectrum Compatible/tracks spreading input requirements, while being backwards compatible to PCIe clock for low EMI Gen2 and Gen1. The 9DB633 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent SMBus Interface/unused outputs can be disabled main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum Output Features: clocking. An SMBus interface allows control of the PLL 6 - 0.7V current mode differential HCSL output pairs bandwidth and bypass options, while 2 clock request (OE ) pins make the 9DB633 suitable for Express Card applications. Key Specifications: Cycle-to-cycle jitter < 50 ps Output-to-output skew < 50 ps PCIe Gen3 phase jitter < 1.0ps RMS Block Diagram OE1 OE4 DIF1 SRC IN SPREAD COMPATIBLE SRC IN PLL DIF4 DIF(0,2,3,5) PLL BW CONTROL SMBDAT LOGIC SMBCLK IREF IDT Six Output Differential Buffer for PCIe Gen3 1668F10/20/16 19DB633 Datasheet Six Output Differential Buffer for PCIe Gen3 Pin Configuration PLL BW 1 28 VDDA SRC IN 2 27 GNDA SRC IN 3 26 IREF vOE1 4 25 vOE4 DIF 0 5 24 DIF 5 DIF 0 6 23 DIF 5 VDD 7 22 VDD GND 8 21 GND DIF 1 9 20 DIF 4 DIF 1 10 19 DIF 4 DIF 2 11 18 DIF 3 DIF 2 12 17 DIF 3 VDD 13 16 VDD SMBDAT 14 15 SMBCLK Pins preceeded by v have internal Note: 120K ohm pull down resistors Power Distribution Table Pin Number Description VDD GND 7, 13, 16, 22 8,21 Differential Outputs 13 8 SMBus N/A 27 IREF 28 27 Analog VDD & GND for PLL core IDT Six Output Differential Buffer for PCIe Gen3 1668F10/20/16 2 9DB633