DATASHEET ICS9DB801C Eight Output Differential Buffer for PCI Express (50-200MHz) Description Features/Benefits Spread spectrum modulation tolerant, 0 to -0.5% down The 9DB801C is a DB800 Version 2.0 Yellow Cover part with PCI Express support. It can be used in PC or embedded spread and +/- 0.25% center spread. systems to provide outputs that have low cycle-to-cycle jitter Supports undriven differential outputs in PD and (50ps), low output-to-output skew (100ps), and are PCI Express SRC STOP modes for power management. gen 1 compliant. The 9DB801C supports a 1 to 8 output Supports polarity inversion to the output enables, configuration, taking a spread or non spread differential HCSL SRC STOP and PD. input from a CK410(B) main clock such as 954101 and 932S401, or any other differential HCSL pair. 9DB801C can Key Specifications generate HCSL or LVDS outputs from 50 to 200MHz in PLL mode or 0 to 400Mhz in bypass mode. There are two de-jittering Outputs cycle-cycle jitter < 50ps modes available selectable through the HIGH BW input pin, Outputs skew: 50ps high bandwidth mode provides de-jittering for spread inputs and 50 - 200MHz operation low bandwidth mode provides extra de-jittering for non-spread Extended frequency range in bypass mode to 400 MHz inputs. The SRC STOP , PD , and individual OE real-time PCI Express Gen I compliant input pins provide completely programmable power Real time PLL lock detect output pin management control. 48-pin SSOP/TSSOP package Output Features Available in RoHS compliant packaging 8 - 0.7V current-mode differential output pairs Supports zero delay buffer mode and fanout mode Bandwidth programming available Funtional Block Diagram 8 OE (7:0) SPREAD SRC IN COMPATIBLE PLL SRC IN M 8 STOP U DIF(7:0)) LOGIC X SRC STOP HIGH BW CONTROL BYPASS /PLL IREF LOGIC PD SDATA LOCK SCLK Note: Polarities shown for OE INV = 0. TM TM IDT /ICS Eight Output Differential Buffer for PCI Express (50-200MHz) 9DB801C REV E 01/27/11 1ICS9DB801C Eight Output Differential Buffer for PCI Express (50-200MHz) Pin Configuration SRC DIV 1 48 VDDA SRC DIV 1 48 VDDA VDD 2 47 GNDA VDD 2 47 GNDA GND 3 46 IREF GND 3 46 IREF SRC IN 4 45 LOCK SRC IN 4 45 LOCK SRC IN 5 44 OE 7 SRC IN 5 44 OE7 643 OE 0 6 43 OE 4 OE0 OE4 OE 3 7 42 DIF 7 OE3 742DIF 7 DIF 0 8 41 DIF 7 DIF 0 8 41 DIF 7 DIF 0 9 40 DIF 0 9 40 OE INV OE INV GND 10 39 VDD GND 10 39 VDD VDD 11 38 DIF 6 VDD 11 38 DIF 6 DIF 1 12 37 DIF 6 DIF 112 37DIF 6 DIF 1 13 36 OE6 DIF 1 13 36 OE 6 14 35 OE1 OE5 OE 1 14 35 OE 5 15 34 DIF 5 OE2 OE 2 15 34 DIF 5 DIF 2 16 33 DIF 5 DIF 216 33DIF 5 DIF 2 17 32 GND DIF 2 17 32 GND GND 18 31 VDD GND 18 31 VDD VDD 19 30 DIF 4 VDD 19 30 DIF 4 DIF 3 20 29 DIF 4 DIF 320 29DIF 4 DIF 3 21 28 HIGH BW DIF 3 21 28 HIGH BW BYPASS /PLL 22 27 SRC STOP BYPASS /PLL 22 27 SRC STOP SCLK 23 26 PD SCLK 23 26 PD SDATA 24 25 GND SDATA 24 25 GND OE INV = 1 OE INV = 0 Polarity Inversion Pin List Table OE INV Pins 01 6OE 0 OE0 7OE 3 OE3 14 OE 1 OE1 15 OE 2 OE2 26 PD PD 27 DIF STOP DIF STOP 35 OE 5 OE5 36 OE 6 OE6 43 OE 4 OE4 44 OE 7 OE7 TM TM IDT /ICS Eight Output Differential Buffer for PCI Express (50-200MHz) 9DB801C REV E 01/27/11 2 ICS9DB801 (Same as ICS9DB108) ICS9DB801