9DB803DFILF Renesas

DATASHEET EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2 ICS9DB803D General Description Features/Benefits The ICS9DB803D is compatible with the Intel DB800v2 Spread spectrum modulation tolerant, 0 to -0.5% down Differential Buffer Specification. This buffer provides 8 spread and +/- 0.25% center spread PCI-Express Gen2 clocks. The ICS9DB803D is driven by a Supports undriven differential outputs in PD and differential output pair from a CK410B+, CK505 or CK509B SRC STOP modes for power management main clock generator. Key Specifications Recommended Application Outputs cycle-cycle jitter < 50ps DB800v2 compatible part with PCIe Gen1 and Gen2 Output to Output skew <50ps Support Phase jitter: PCIe Gen1 < 86ps peak to peak Phase jitter: PCIe Gen2 < 3.0/3.1ps rms Output Features 8 - 0.7V current-mode differential output pairs Supports zero delay buffer mode and fanout mode Bandwidth programming available 50-100 MHz operation in PLL mode 50-400 MHz operation in Bypass mode Functional Block Diagram 8 OE (7:0) SPREAD SRC IN COMPATIBLE PLL SRC IN M 8 STOP U DIF(7:0)) LOGIC X SRC STOP HIGH BW CONTROL BYPASS /PLL IREF LOGIC PD SDATA LOC K SCLK Note: Polarities shown are for OE INV=0. IDT EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2 1 ICS9DB803D REV N 071013ICS9DB803D EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2 Pin Configuration SRC DIV 1 48 VDDA SRC DIV 1 48 VDDA VDDR 2 47 GNDA VDDR 2 47 GNDA GND 3 46 IREF GND 3 46 IREF SRC IN 4 45 LOCK SRC IN 4 45 LOCK SRC IN 5 44 OE 7 SRC IN 5 44 OE7 OE 0 6 43 OE 4 OE0 643 OE4 OE 3 7 42 DIF 7 742DIF 7 OE3 DIF 0 8 41 DIF 7 DIF 0 8 41 DIF 7 DIF 0 9 40 OE INV DIF 0 9 40 OE INV GND 10 39 VDD GND 10 39 VDD VDD 11 38 DIF 6 VDD 11 38 DIF 6 DIF 112 37DIF 6 DIF 112 37DIF 6 DIF 1 13 36 OE 6 DIF 1 13 36 OE6 OE 1 14 35 OE 5 OE1 14 35 OE5 OE 2 15 34 DIF 5 OE2 15 34 DIF 5 DIF 216 33DIF 5 DIF 216 33DIF 5 DIF 2 17 32 GND DIF 2 17 32 GND GND 18 31 VDD GND 18 31 VDD VDD 19 30 DIF 4 VDD 19 30 DIF 4 DIF 320 29DIF 4 DIF 320 29DIF 4 DIF 3 21 28 HIGH BW DIF 3 21 28 HIGH BW BYPASS /PLL 22 27 DIF STOP BYPASS /PLL 22 27 DIF STOP SCLK 23 26 PD SCLK 23 26 PD SDATA 24 25 GND SDATA 24 25 GND OE INV = 0 OE INV = 1 Power Groups Pin Number Description VDD GND 2 3 SRC IN/SRC IN 6,11,19, 10,18, 25,32 DIF(7:0) 31,39 N/A 47 IREF 48 47 Analog VDD & GND for PLL core Polarity Inversion Pin List Table OE INV Pins 01 6OE 0 OE 0 7OE 3 OE 3 14 OE 1 OE 1 15 OE 2 OE 2 26 PD PD 27 DIF STOP DIF STOP 35 OE 5 OE 5 36 OE 6 OE 6 43 OE 4 OE 4 44 OE 7 OE 7 IDT EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2 2 ICS9DB803D REV N 071013 ICS9DB803 (Same as ICS9DB108) ICS9DB803 (Same as ICS9DB801)