DATASHEET EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN13 9DB833 Description Features The 9DB833 zero-delay buffer supports PCIe Gen3 3 selectable SMBus addresses multiple devices can requirements, while being backwards compatible to PCIe share the same SMBus segment Gen2 and Gen1. The 9DB833 is driven by a differential OE pins suitable for Express Card applications SRC output pair from an IDT 932S421 or 932SQ420 or PLL or bypass mode PLL can dejitter incoming clock equivalent main clock generator. Selectable PLL bandwidth minimizes jitter peaking in downstream PLLs Typical Applications Spread spectrum compatible tracks spreading input 8 output PCIe Gen13 zero delay/fanout buffer clock for low EMI Output Features SMBus interface unused outputs can be disabled Supports undriven differential outputs in Power Down 8 0.7V current-mode differential HCSL output pairs mode for power management Supports zero delay buffer mode and fanout mode Selectable bandwidth Key Specifications 50110MHz operation in PLL mode Outputs cycle-cycle jitter <50ps 5166MHz operation in Bypass mode Output to output skew <50ps Phase jitter: PCIe Gen3 <1.0ps rms Block Diagram 8 OE(7:0) SPREAD SRC IN COMPATIBLE PLL SRC IN M 8 STOP DIF(7:0)) U LOGIC X PD CONTROL BYP LOBW HIBW IREF LOGIC SMBDAT LOCK SMBCLK IDT EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN13 1 9DB833 MAY 25, 20189DB833 EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN13 Pin Configuration SRC DIV 1 48 VDDA VDDR 2 47 GNDA GND 3 46 IREF SRC IN 4 45 LOCK SRC IN 5 44 OE7 OE0 643 OE4 OE3 742DIF 7 DIF 0 8 41 DIF 7 940 PD DIF 0 GND 10 39 VDD VDD 11 38 DIF 6 12 37 DIF 1 DIF 6 OE6 DIF 1 13 36 OE1 14 35 OE5 OE2 15 34 DIF 5 DIF 2 16 33 DIF 5 17 32 GND DIF 2 GND 18 31 VDD VDD 19 30 DIF 4 20 29 DIF 3 DIF 4 DIF 3 21 28 SMB ADR tri BYP HIBW LOBW 22 27 VDD GND SMBCLK 23 26 24 25 GND SMBDAT Notes: Highlighted Pins are the differences between 9DB803 and 9DB833. Pin 22 and Pin 28 are latched on power up. Please make sure that the power supply to the pullup/pulldown resistors ramps at the same time as the main supply to the chip. Operating Mode Readback Table BYP LOBW HIBW MODE Byte0, bit 3 Byte 0 bit 1 Low Bypass 0 0 Mid PLL 100M Hi BW 1 0 High PLL 100M Low BW 0 1 Power Connections SMBus Address Selection and Readback SMB ADR tri Address Pin Number Description Low DA/DB VDD GND Mid DC/DD 2 3 SRC IN/SRC IN High D8/D9 11,19,31,39 10,18, 25,32 DIF(7:0) 27 26 DIGITAL VDD/GND 48 47 Analog VDD/GND for PLL in IREF For best results, treat pin 2 as analog VDD. Tri-level Input Logic Levels State of Pin Voltage Low <0.8V Mid 1.2<Vin<1.8V High Vin > 2.0V IDT EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN13 2 9DB833 MAY 25, 2018 9DB833