9DBL0255NLGI Renesas

2 and 4-Output 3.3V PCIe Gen15 9DBL0255/9DBL0455 Clock Fanout Buffers with LOS Datasheet Description Features FPS: VDD may be applied with floating input clock, or input The 9DBL0255/9DBL0455 are 2 and 4-output PCIe Clock fan-out clock may be driven before VDD is applied buffers for PCIe Gen1-5 applications. Both parts have an open drain Loss of Signal (LOS) output to indicate the absence or ACP: Outputs automatically park low/low when LOS occurs presence of an input clock. The LOS circuit also implements and cleanly start when LOS is removed Automatic Clock Parking (ACP) to cleanly park the outputs PDT: Input pins may be driven before VDD is applied and will low/low when the input clock goes away. The devices implement not damage the device several additional features to aid robust designs. Flexible Power 2 or 4 Low-power HCSL (LP-HCSL) DIF pairs Sequencing (FPS) ensures well-defined behavior under various 85 loads require 0 termination resistors power up scenarios, while Power Down Tolerant (PDT) ESD protection allows input pins to be driven before VDD is applied. 100 loads require only 2 series resistors per output The 9DBL0255/9DBL0455 are spread-spectrum compatible and OE pin for each output provide direct connection to 85 transmission lines. They can also Spread-spectrum tolerant be used in 100 environments with simple external series Industrial temperature range (-40C to +85C) resistors. Space saving 3 3 mm 16-VFQFPN (9DBL0255) PCIe Architectures Space saving 4 4 mm 20-VFQFPN (9DBL0455) Easy AC-coupling to other logic families. See application note Common Clocked (CC) AN-891. Independent Reference Clock (SRIS, SRnS) Key Specifications Typical Applications Input-to-output delay < 3ns PCIe clock distribution in: Output-to-output skew < 50ps PCIe Riser Cards Operating frequency up to 267MHz (9DBL0455) NVME eSSD and JBOD Additive phase jitter < 15fs RMS for PCIe Gen5 High-Performance Computing and Accelerators Additive phase jitter 46fs RMS (typical) at 156.25MHz (12kHz20MHz) Block Diagram DIF0 0.5V DIF0 50K DIF1 CLK IN DIF1 CLK IN DIF2 50K DIF2 9DBL0455 only DIF3 9DBL0455 DIF3 vOE 3:2 only LOS and OE vOE 1:0 Logic 9DBL0255 LOS vTEST EN only 2021 Renesas Electronics Corporation 1 March 17, 20219DBL0255/9DBL0455 Datasheet Contents Description 1 PCIe Architectures 1 Typical Applications . 1 Features 1 Key Specifications 1 Block Diagram . 1 Pin Assignments 3 9DBL0255 Pin Descriptions . 4 9DBL0455 Pin Descriptions . 4 Power Management . 5 Absolute Maximum Ratings . 6 Thermal Characteristics 6 Electrical Characteristics . 7 Test Loads . 11 Alternate Terminations 11 Package Outline Drawings . 12 Marking Diagrams . 12 Ordering Information . 12 Revision History . 13 2021 Renesas Electronics Corporation 2 March 17, 2021