9-Output 3.3V PCIe Fanout Buffer 9DBL09x1 DATASHEET Description Features/Benefits The 9DBL09x1 devices are 3.3V members of IDT s Direct connection to 100 (xx41) or 85 (xx51) Full-Featured PCIe clock family. The 9DBL09x1 devices transmission lines saves 36 resistors compared to support PCIe Gen14 Common Clocked (CC) and PCIe standard PCIe devices Separate Reference Independent Spread (SRIS) systems. 165mW typical power consumption (at 3.3V) eliminates They offer a choice of integrated output terminations thermal concerns providing direct connection to 85 or 100 transmission VDDIO allows 50% power savings at optional 1.05V lines. The 9DBL09P1 can be factory programmed with a maximum power savings user-defined power up default SMBus configuration. SMBus-selectable features allows optimization to customer requirements: Recommended Application control input polarity PCIe Gen14 clock distribution for Riser Cards, Storage, control input pull up/downs Networking, JBOD, Communications, Access Points slew rate for each output Output Features differential output amplitude 9 1-200 MHz Low-Power (LP) HCSL DIF pairs output impedance for each output 9DBL0941 default Zout = 100 Customer defined SMBus power up default can be programmed into P1 device allows exact optimization to 9DBL0951 default Zout = 85 customer requirements 9DBL09P1 factory programmable defaults OE pins support DIF power management Easy AC-coupling to other logic families, see IDT HCSL differential input can be driven by common clock application note AN-891. sources Key Specifications Spread spectrum tolerant allows reduction of EMI DIF additive cycle-to-cycle jitter < 5ps Device contains default configuration SMBus interface not required for device operation DIF output-to-output skew < 50ps Three selectable SMBus addresses multiple devices can Additive phase jitter is 0ps (typical rms) for PCIe Gen14 easily share an SMBus segment CC, SRIS Space saving 48-pin 6 x 6mm VFQFPN minimal board Additive phase jitter 111fs rms typical at 156.25M (1.5M to space 10M) Block Diagram vOE(8:0) 9 DIF8 DIF7 DIF6 CLK IN DIF5 CLK IN DIF4 vSADR DIF3 DIF2 CKPW RGD PD SDATA 3.3 DIF1 SCLK 3.3 DIF0 Note: Resistors default to internal on 41/51 devices. P1 devices have programmable default impedances on an output-by-output basis. 9DBL09x1 AUGUST 1, 2017 1 2017 Integrated Device Technology, Inc. Control Logic9DBL09x1 DATASHEET Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 vSADR tri 1 36 DIF5 vOE8 2 35 DIF5 DIF8 3 34 vOE4 DIF8 4 33 DIF4 VDDR3.3 5 32 DIF4 CLK IN 6 31 VDDIO 9DBL09x1 CLK IN 7 30 VDD3.3 epad is GND GNDR 8 29 GNDA GNDDIG 9 28 vOE3 SCLK 3.3 10 27 DIF3 SDATA 3.3 11 26 DIF3 VDDDIG3.3 12 25 vOE2 13 14 15 16 17 18 19 20 21 22 23 24 48-pin VFQFPN, 6x6 mm, 0.4mm pitch v prefix indicates internal 120KOhm pull up AND pull down resistor (biased to VDD/2) v prefix indicates internal 120KOhm pull down resistor prefix indicates internal 120KOhm pull up resistor SMBus Address Selection Table + Read/Write bit SADR Address State of SADR on first 0 1101011 x application of M 1101100 x CKPWRGD PD 1 1101101 x Note: If not using CKPWRGD (i.e., CKPWRGD tied to VDD3.3), all 3.3V VDD need to transition from 2.1V to 3.135V in <300usec. Power Management Table DIFx SMBus CKPWRGD PD CLK IN OEx Pin OEx bit True O/P Comp. O/P 1 1 0X X X Low Low 1 1 1 Running 0 X Low Low 1 Running 1 0 Running Running 1 1 1 Running 1 1 Low Low 1. The output state is set by B11 1:0 (Low/Low default) Power Connections Pin Number Description VDD VDDIO GND Input 58 receiver analog 12 9 Digital Power 20,30,31,38 13,21,31,39,47 22,29,40,49 DIF outputs 9-OUTPUT 3.3V PCIE FANOUT BUFFER 2 AUGUST 1, 2017 VDDIO CKPWRGD PD vOE0 VDDIO DIF0 vOE7 DIF0 DIF7 vOE1 DIF7 DIF1 vOE6 DIF1 DIF6 VDD3.3 DIF6 VDDIO GND GND VDDIO DIF2 VDD3.3 DIF2 vOE5