9DBU0431AKLF Renesas

4 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB 9 D B U 04 3 1 D A T A S H E E T Description Features/Benefits The 9DBU0431 is a member of IDT s 1.5V Ultra-Low-Power LP-HCSL outputs save 8 resistors compared to standard (ULP) PCIe family. The device has 4 output enables for clock HCSL outputs management, and 3 selectable SMBus addresses. 45mW typical power consumption in PLL mode eliminates thermal concerns Recommended Application Spread Spectrum (SS) compatible allows SS for EMI 1.5V PCIe Gen1-2-3 Zero-Delay/Fan-out Buffer (ZDB/FOB) reduction OE pins support DIF power management Output Features HCSL-compatible differential input can be driven by 4 1-167MHz Low-Power (LP) HCSL DIF pairs common clock sources SMBus-selectable features optimize signal integrity to Key Specifications application DIF cycle-to-cycle jitter <50ps slew rate for each output DIF output-to-output skew <50ps differential output amplitude DIF phase jitter is PCIe Gen1-2-3 compliant Pin/software selectable PLL bandwidth and PLL Bypass DIF bypass mode additive phase jitter is <300fs rms for optimize PLL to application PCIe Gen3 Outputs blocked until PLL is locked clean system start-up DIF bypass mode additive phase jitter <350fs rms for Device contains default configuration SMBus interface not 12k-20MHz required for device control 3.3V tolerant SMBus interface works with legacy controllers Three selectable SMBus addresses multiple devices can easily share an SMBus segment Space saving 32-pin 5x5mm VFQFPN minimal board space Block Diagram vOE(3:0) 4 CLK IN DIF3 SS- DIF2 Compatible PLL DIF1 vSADR DIF0 vHIBW BYPM LOBW CONTROL CKPWRGD PD LOGIC SDATA 3.3 SCLK 3.3 9DBU0431 REVISION C 04/22/15 1 2014 Integrated Device Technology, Inc. CLK IN 9DBU0431 DATASHEET Pin Configuration GNDR GNDDIG SMBus Address Selection Table SADR Address + Read/Write bit x 0 1101011 State of SADR on first application of x M 1101100 CKPWRGD PD 1 1101101 x Power Management Table SMBus DIFx CKPWRGD PD CLK IN OEx Pin PLL OEx bit True O/P Comp. O/P 0 X X X Low Low Off 1 1 Running 0 X Low Low On 1 1 Running 1 0 Running Running On 1 1 Running 1 1 Low Low On 1. If Bypass mode is selected, the PLL will be off, and outputs will be running. Power Connections PLL Operating Mode Note: epad on this device is not electrically connected to the die. It should be connected to ground for best thermal performance. 4 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB 2 REVISION C 04/22/15