9DBU0441AKILF Renesas

4 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB 9D B U 0441 w/Zo=100ohms D A T A S H E E T Description Features/Benefits The 9DBU0441 is a member of IDT s 1.5V Ultra-Low-Power Direct connection to 100 transmission lines saves 16 (ULP) PCIe family. It has integrated output terminations resistors compared to standard HCSL outputs providing Zo=100 for direct connection to 100 45mW typical power consumption in PLL mode eliminates transmission lines. The device has 4 output enables for clock thermal concerns management, and 3 selectable SMBus addresses. Spread Spectrum (SS) compatible allows SS for EMI reduction Recommended Application OE pins support DIF power management 1.5V PCIe Gen1-2-3 Zero-Delay/Fan-out Buffer (ZDB/FOB) HCSL-compatible differential input can be driven by common clock sources Output Features SMBus-selectable features optimize signal integrity to 4 1-167MHz Low-Power (LP) HCSL DIF pairs application w/ZO=100 slew rate for each output Key Specifications differential output amplitude Pin/software selectable PLL bandwidth and PLL Bypass DIF cycle-to-cycle jitter <50ps optimize PLL to application DIF output-to-output skew <75ps Outputs blocked until PLL is locked clean system start-up DIF phase jitter is PCIe Gen1-2-3 compliant Device contains default configuration SMBus interface not DIF bypass mode ad di t ive phase jitter is <300fs rms for required for device control PCIe Gen3 3.3V tolerant SMBus interface works with legacy controllers DIF bypass mode ad di t ive phase jitter <350fs rms for Three selectable SMBus addresses multiple devices can 12k-20MHz easily share an SMBus segment Space saving 32-pin 5x5mm VFQFPN minimal board space Block Diagram vOE(3:0) 4 CLK IN DIF3 CLK IN SS- DIF2 Compatible PLL DIF1 vSADR DIF0 vHIBW BYPM LOBW CONTROL CKPWRGD PD LOGIC SDATA 3.3 SCLK 3.3 9DBU0441 REVISION C 04/22/15 19DBU0441 DATASHEET Pin Configuration GNDR GNDDIG SMBus Address Selection Table SADR Address + Read/Write bit x 0 1101011 State of SADR on first application of x M 1101100 CKPWRGD PD 1 1101101 x Power Management Table SMBus DIFx CKPWRGD PD CLK IN OEx Pin PLL OEx bit True O/P Comp. O/P 0 X X X Low Low Off 1 1 Running 0 X Low Low On 1 1 Running 1 0 Running Running On 1 1 Running 1 1 Low Low On 1. If Bypass mode is selected, the PLL will be off, and outputs will be running. Power Connections PLL Operating Mode Note: epad on this device is not electrically connected to the die. It should be connected to ground for best thermal performance. 4 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS 2 REVISION C 04/22/15