5-Output 1.5V PCIe Gen1-2-3 Fanout Buffer 9DBU0531 DATASHEET Description Features/Benefits The 9DBU0531 is a member of IDT s 1.5V Ultra-Low-Power LP-HCSL outputs save 10 resistors compared to standard (ULP) PCIe family. The device has 5 output enables for clock HCSL outputs management, and 3 selectable SMBus addresses. 35mW typical power consumption eliminates thermal concerns Recommended Application Spread Spectrum (SS) compatible allows SS for EMI 1.5V PCIe Gen1-2-3 Fanout Buffer (FOB) reduction OE pins for each output support DIF power management Output Features HCSL-compatible differential input can be driven by 5 1167MHz Low-Power (LP) HCSL DIF pairs common clock sources Spread Spectrum tolerant allows reduction of EMI Key Specifications SMBus-selectable features optimize signal integrity to DIF additive cycle-to-cycle jitter < 5ps application DIF output-to-output skew < 60ps slew rate for each output DIF additive phase jitter is < 300fs rms for PCIe Gen3 differential output amplitude DIF additive phase jitter < 350fs rms for SGMII Device contains default configuration SMBus interface not required for device operation 3.3V tolerant SMBus interface works with legacy controllers 3 selectable SMBus addresses multiple devices can easily share an SMBus segment 5 5 mm 32-VFQFPN minimal board space Block Diagram , vOE(4:0) 5 DIF4 CLK IN DIF3 CLK IN DIF2 vSADR DIF1 CKPWRGD PD CONTROL DIF0 LOGIC SDATA 3.3 SCLK 3.3 9DBU0531 MARCH 9, 2017 1 2017 Integrated Device Technology, Inc.9DBU0531 DATASHEET Pin Configuration 32 31 30 29 28 27 26 25 vOE4 1 vOE2 24 DIF4 2 DIF2 23 DIF4 3 DIF2 22 VDDR1.5 4 VDDO1.5 21 9DBU0531 CLK IN 5 20 GND epad is GND CLK IN 6 DIF1 19 GNDR 7 18 DIF1 GNDDIG 817vOE1 9 10 111213141516 32-pin VFQFPN, 5x5 mm, 0.5mm pitch prefix indicates internal 120KOhm pull up resistor v prefix indicates internal 120KOhm pull up AND pull down resistor (biased to VDD/2) v prefix indicates internal 120KOhm pull down resistor SMBus Address Selection Table SADR Address + Read/Write bit x 0 1101011 State of SADR on first application of x M 1101100 CKPWRGD PD 1 1101101 x Power Management Table SMBus DIFx CKPWRGD PD CLK IN OEx Pin OEx bit True O/P Comp. O/P 0X X X Low Low 1 Running 0 X Low Low 1 Running 1 0 Running Running 1 Running 1 1 Low Low Power Connections Pin Number Description VDD GND 47 Input receiver analog 98 Digital power 16, 21, 25 15,20,26,30 DIF outputs Note: EPAD on this device is not electrically connected to the die. It should be connected to ground for best thermal performance. 5-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER 2 MARCH 9, 2017 VDDDIG1.5 SADR tri SCLK 3.3 CKPWRGD PD SDATA 3.3 GND vOE0 vOE3 DIF0 DIF3 DIF0 DIF3 GND GND VDDO1.5 VDDO1.5