9DBU0541AKILF Renesas

5-Output 1.5V PCIe Gen1-2-3 Fanout Buffer 9DBU0541 with Zo=100ohms DATASHEET Description Features/Benefits The 9DBU0541 is a member of IDT s 1.5V Ultra-Low-Power Integrated terminations save 20 resistors compared to (ULP) PCIe family. It has integrated terminations for direct standard HCSL outputs connection to 100 transmission lines. The device has 5 35mW typical power consumption eliminates thermal output enables for clock management, and 3 selectable concerns SMBus addresses. Spread Spectrum (SS) compatible allows SS for EMI reduction Recommended Application OE pins support DIF power management 1.5V PCIe Gen1-2-3 Fanout Buffer (FOB) HCSL-compatible differential input can be driven by common clock sources Output Features SMBus-selectable features optimize signal integrity to 5 1167MHz Low-Power (LP) HCSL DIF pairs with application Z =100 O slew rate for each output Key Specifications differential output amplitude Device contains default configuration SMBus interface not DIF additive cycle-to-cycle jitter < 5ps required for device control DIF output-to-output skew < 60ps 3.3V tolerant SMBus interface works with legacy controllers DIF additive phase jitter is < 300fs rms for PCIe Gen3 Selectable SMBus addresses multiple devices can easily DIF additive phase jitter < 350fs rms for SGMII share an SMBus segment 5 5 mm 32-VFQFPN minimal board space Block Diagram vOE(4:0) 5 CLK IN DIF4 CLK IN DIF3 vSADR DIF2 DIF1 CKPWRGD PD CONTROL LOGIC SDATA 3.3 DIF0 SCLK 3.3 9DBU0541 MARCH 9, 2017 1 2017 Integrated Device Technology, Inc.9DBU0541 DATASHEET Pin Configuration 32 31 30 29 28 27 26 25 vOE4 1 vOE2 24 DIF4 2 DIF2 23 DIF4 3 DIF2 22 VDDR1.5 4 VDDO1.5 21 9DBU0541 CLK IN 5 GND 20 epad is GND CLK IN 6 DIF1 19 GNDR 7 DIF1 18 GNDDIG 817vOE1 9 101112 13141516 32-pin VFQFPN, 5x5 mm, 0.5mm pitch prefix indicates internal 120KOhm pull up resistor v prefix indicates internal 120KOhm pull up AND pull down resistor (biased to VDD/2) v prefix indicates internal 120KOhm pull down resistor SMBus Address Selection Table + Read/Write bit SADR Address 0 1101011 x State of SADR on first application of M 1101100 x CKPWRGD PD 1 1101101 x Power Management Table SMBus DIFx CKPWRGD PD CLK IN OEx Pin OEx bit True O/P Comp. O/P 0X X X Low Low 1 Running 0 X Low Low 1 Running 1 0 Running Running 1 Running 1 1 Low Low Power Connections Pin Number Description VDD GND 47 Input receiver analog 98 Digital power 16, 21, 25 15,20,26,30 DIF outputs Note: EPAD on this device is not electrically connected to the die. It should be connected to ground for best thermal performance. 5-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS 2 MARCH 9, 2017 VDDDIG1.5 SADR tri SCLK 3.3 CKPWRGD PD SDATA 3.3 GND vOE0 vOE3 DIF0 DIF3 DIF0 DIF3 GND GND VDDO1.5 VDDO1.5