9DBU0641AKILF Renesas

6 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB 9D B U 0641 w/Zo=100ohms D A T A S H E E T Description Features/Benefits The 9DBU0641 is a member of IDT s 1.5V Ultra-Low-Power Direct connection to 100 transmission lines saves 24 (ULP) PCIe family. It has integrated output terminations resistors compared to standard HCSL outputs providing Zo=100 for direct connection to 100 46mW typical power consumption in PLL mode eliminates transmission lines. The device has 6 output enables for clock thermal concerns management and 3 selectable SMBus addresses. Outputs can optionally be supplied from any voltage between 1.05 and 1.5V maximum power savings Recommended Application Spread Spectrum (SS) compatible allows SS for EMI 1.5V PCIe Gen1-2-3 Zero Delay/Fanout Buffer (ZDB/FOB) reduction OE pins support DIF power management Output Features HCSL-compatible differential input can be driven by 6 1-167MHz Low-Power (LP) HCSL DIF pairs common clock sources w/Zo=100 SMBus-selectable features optimize signal integrity to application Key Specifications slew rate for each output DIF cycle-to-cycle jitter <50ps differential output amplitude DIF output-to-output skew <60ps Pin/SMBus selectable PLL bandwidth and PLL Bypass DIF phase jitter is PCIe Gen1-2-3 compliant optimze PLL to application DIF bypass mode ad di t ive phase jitter is <300fs rms for Outputs blocked until PLL is locked clean system start-up PCIe Gen3 Device contains default configuration SMBus interface not DIF bypass mode ad di t ive phase jitter <350fs rms for required for device control 12k-20MHz 3.3V tolerant SMBus interface works with legacy controllers Three selectable SMBus addresses multiple devices can easily share an SMBus segment Space saving 40-pin 5x5mm VFQFPN minimal board space Block Diagram vOE(5:0) 6 DIF5 CLK IN CLK IN SS- DIF4 Compatible DIF3 PLL vSADR DIF2 vHIBW BYPM LOBW DIF1 CONTROL CKPWRGD PD LOGIC DIF0 SDATA 3.3 SCLK 3.3 9DBU0641 REVISION C 04/22/15 19DBU0641 DATASHEET Pin Configuration 40-VFQFPN, 5mm x 5mm 0.4mm pin pitch prefix indicates internal 120KOhm pull up resistor v prefix indicates internal 120KOhm pull up AND pull down resistor (biased to VDD/2) v prefix indicates internal 120KOhm pull down resistor SMBus Address Selection Table SADR Address + Read/Write bit x 0 1101011 State of SADR on first application of x M 1101100 CKPWRGD PD 1 1101101 x Power Management Table SMBus DIFx CKPWRGD PD CLK IN OEx Pin PLL OEx bit True O/P Comp. O/P 0 X X X Low Low Off 1 1 Running 0 X Low Low On 1 1 Running 1 0 Running Running On 1 1 Running 1 1 Low Low On 1. If Bypass mode is selected, the PLL will be off, and outputs will follow this table. Power Connections PLL Operating Mode 6 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS 2 REVISION C 04/22/15