7-Output 1.5V PCIe Gen1-2-3 Fanout Buffer 9DBU0741 with Zo=100ohms DATASHEET Description Features/Benefits The 9DBU0741 is a member of IDT s 1.5V Ultra-Low-Power Integrated terminations save 28 resistors compared to (ULP) PCIe family. It has integrated terminations for direct standard HCSL outputs connection to 100 transmission lines. The device has 7 36mW typical power consumption eliminates thermal output enables for clock management, and 3 selectable concerns SMBus addresses. Outputs can optionally be supplied from any voltage between 1.05V and 1.5V maximum power savings Recommended Application Spread Spectrum (SS) compatible allows SS for EMI 1.5V PCIe Gen1-2-3 Fanout Buffer (FOB) reduction OE pins for each output support DIF power management Output Features HCSL-compatible differential input can be driven by 7 1167MHz Low-Power (LP) HCSL DIF pairs with common clock sources Zo=100 SMBus-selectable features optimize signal integrity to application Key Specifications slew rate for each output DIF additive cycle-to-cycle jitter < 5ps differential output amplitude DIF output-to-output skew < 60ps Device contains default configuration SMBus interface not DIF additive phase jitter is < 300fs rms for PCIe Gen3 required for device operation DIF additive phase jitter < 350s rms for SGMII Selectable SMBus addresses multiple devices can easily share an SMBus segment 3.3V tolerant SMBus interface works with legacy controllers 5 5 mm 40-VFQFPN package minimal board space Block Diagram vOE(6:0) 7 DIF6 CLK IN DIF5 CLK IN DIF4 DIF3 vSADR DIF2 CKPWRGD PD CONTROL LOGIC DIF1 SDATA 3.3 SCLK 3.3 DIF0 9DBU0741 MARCH 8, 2017 1 2017 Integrated Device Technology, Inc.9DBU0741 DATASHEET Pin Configuration 40 39 38 37 36 35 34 33 32 31 vSADR tri NC 130 vOE6 vOE3 229 DIF6 DIF3 328 DIF6 DIF3 427 VDDR1.5 9DBU0741 VDDIO 526 CLK IN VDDO1.5 625 epad is GND CLK IN vOE2 724 GNDDIG DIF2 823 SCLK 3.3 DIF2 922 SDATA 3.3 vOE1 10 21 11 12 13 14 15 16 17 18 19 20 40-VFQFPN prefix indicates internal Pull-Up Resistor v prefix indicates Internal Pull-Dow n Resistor 5mm x 5mm 0.4mm pin pitch SMBus Address Selection Table + Read/Write bit SADR Address x 0 1101011 State of SADR on first application of x M 1101100 CKPWRGD PD 1 1101101 x Power Management Table SMBus DIFx CKPWRGD PD CLK IN OEx Pin OEx bit True O/P Comp. O/P 0X X X LowLow 1 Running 0 X Low Low 1 Running 1 0 Running Running 1 Running 1 1 Low Low Power Connections Pin Number Description VDD VDDIO GND Input 541 receiver analog 11 8 Digital power 12,17,26,32, DIF outputs, 16,25,31 41 39 Logic 7-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS 2 MARCH 8, 2017 VDDDIG1.5 CKPWRGD PD VDDIO VDDIO vOE0 vOE5 DIF0 DIF5 DIF0 DIF5 VDD1.5 vOE4 VDDIO DIF4 DIF1 DIF4 DIF1 VDDIO NC VDD1.5