8 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB 9DBU0831 DATASHEET Description Features/Benefits The 9DBU0831 is a member of IDT s 1.5V Ultra-Low-Power LP-HCSL outputs save 16 resistors compared to standard (ULP) PCIe family. The device has 8 output enables for clock HCSL outputs management and 3 selectable SMBus addresses. 53mW typical power consumption in PLL mode eliminates thermal concerns Recommended Application Outputs can optionally be supplied from any voltage 1.5V PCIe Gen1-2-3 Zero Delay/Fanout Buffer (ZDB/FOB) between 1.05 and 1.5V maximum power savings Spread Spectrum (SS) compatible allows SS for EMI Output Features reduction 8 1-167MHz Low-Power (LP) HCSL DIF pairs OE pins support DIF power management HCSL-compatible differential input can be driven by Key Specifications common clock sources DIF cycle-to-cycle jitter <50ps SMBus-selectable features optimize signal integrity to DIF output-to-output skew < 75ps application DIF phase jitter is PCIe Gen1-2-3 compliant slew rate for each output DIF bypass mode additive phase jitter is <300fs rms for differential output amplitude PCIe Gen3 Pin/SMBus selectable PLL bandwidth and PLL Bypass DIF bypass mode additive phase jitter <350fs rms for optimize PLL to application 12k-20MHz Outputs blocked until PLL is locked clean system start-up Device contains default configuration SMBus interface not required for device control Three selectable SMBus addresses multiple devices can easily share an SMBus segment 3.3V tolerant SMBus interface works with legacy controllers Space saving 48-pin 6x6mm VFQFPN minimal board space Block Diagram vOE(7:0) 8 DIF7 DIF6 CLK IN SS- DIF5 Compatible PLL DIF4 vSADR DIF3 vHIBW BYPM LOBW CONTROL DIF2 CKPWRGD PD LOGIC SDATA 3.3 DIF1 SCLK 3.3 DIF0 9DBU0831 REVISION C 04/22/15 1 2015 Integrated Device Technology, Inc. CLK IN 9DBU0831 DATASHEET Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 vSADR tri 1 36 DIF5 vHIBW BYPM LOBW 2 35 DIF5 FB DNC 3 34 vOE4 FB DNC 4 33 DIF4 VDDR1.5 5 32 DIF4 CLK IN 6 31 VDDIO 9DBU0831 CLK IN 7 30 VDDA1.5 epad is GND GNDR 8 29 GNDA GNDDIG 9 28 vOE3 SCLK 3.3 10 27 DIF3 SDATA 3.3 11 26 DIF3 VDDDIG1.512 25vOE2 13 14 15 16 17 18 19 20 21 22 23 24 48-pin MLF, 6x6 mm, 0.4mm pitch v prefix indicates internal 120KOhm pull up AND pull down resistor (biased to VDD/2) v prefix indicates internal 120KOhm pull down resistor prefix indicates internal 120KOhm pull up resistor SMBus Address Selection Table + Read/Write bit SADR Address 0 1101011 x State of SADR on first application of M 1101100 x CKPWRGD PD 1 1101101 x Power Management Table SMBus DIFx CKPWRGD PD CLK IN OEx Pin PLL OEx bit True O/P Comp. O/P 0 X X X Low Low Off 1 1 Running 0 X Low Low On 1 1 Running 1 0 Running Running On 1 1 Running 1 1 Low Low On 1. If Bypass mode is selected, the PLL will be off, and outputs will be running. Power Connections PLL Operating Mode Pin Number Byte1 7:6 Byte1 4:3 Description VDD VDDIO GND HiBW BypM LoBW MODE Readback Control Input 0 PLL Lo BW 00 00 58 receiver MBypass 01 01 analog 1 PLL Hi BW 11 11 12 9 Digital Power 13,21,31,39, 20,31,38 22,29,40 DIF outputs 47 30 29 PLL Analog Note: epad on this device is not electrically connected to the die. It should be connected to ground for best thermal performance. 8 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB 2 REVISION C 04/22/15 VDDIO CKPWRGD PD vOE0 VDDIO DIF0 vOE7 DIF0 DIF7 vOE1 DIF7 DIF1 vOE6 DIF1 DIF6 VDD1.5 DIF6 VDDIO GND GND VDDIO DIF2 VDD1.5 DIF2 vOE5